Lines Matching defs:Reg
732 unsigned Reg = MO.getReg();
733 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
734 if (!OpRegCstraints->contains(Reg))
736 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
737 !MRI->constrainRegClass(Reg, OpRegCstraints))
992 unsigned Reg = MI->getOperand(0).getReg();
1000 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
1002 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1003 .addReg(Reg, RegState::Kill).addImm(0)
1006 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
1008 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1009 .addReg(Reg, RegState::Kill)
1011 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1012 .addReg(Reg, RegState::Kill)
1014 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1015 .addReg(Reg, RegState::Kill)
1017 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1018 .addReg(Reg, RegState::Kill).addImm(0)
1021 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
1024 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1025 .addReg(Reg, RegState::Kill)
1505 unsigned Reg, unsigned SubIdx,
1509 return MIB.addReg(Reg, State);
1511 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1512 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1513 return MIB.addReg(Reg, State, SubIdx);