Lines Matching defs:SRA
667 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
1602 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1630 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
2305 case ISD::SRA:
4403 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4438 Opc == ISD::SRA
6554 case ISD::SRA:
6559 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6567 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
7345 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7349 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
7404 SDValue SRA =
7405 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
7410 return SRA;
7413 Created->push_back(SRA.getNode());
7414 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
9480 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
9545 case ISD::SRA: