Lines Matching defs:width
780 assert(BitWidth >= 8 && "Unexpected width!");
784 assert(BitWidth >= 16 && "Unexpected width!");
4434 // AArch64 shifts larger than the register width are wrapped rather than
4914 // the original, but with a total width matching the BUILD_VECTOR output.
5955 // be truncated to fit element width.
7533 // Only optimize when the source and destination types have the same width.
7542 // Do not change the width of a volatile load.
7998 // The vector width should be 128 bits by the time we get here, even
9181 // Checks to see if the value is the prescribed width and returns information
9184 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
9191 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
9192 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
9200 if ((TypeNode->getVT() == MVT::i8 && width == 8)
9201 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
9209 if ((TypeNode->getVT() == MVT::i8 && width == 8)
9210 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
9219 1LL << (width - 1))
9256 // width of the input (this can work for any width inputs, the above graph is
9290 bool isEquivalentMaskless(unsigned CC, unsigned width,
9296 signed MaxUInt = (1 << width);
9300 // width. Provided we are careful and make sure our equations are valid over
9304 AddConstant -= (1 << (width-1));