config/sparc/sparc.c

1000       && (SPARC_FP_REG_P (REGNO (operands[0]))
1011       if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
1015       if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
1117       temp = gen_rtx_REG (DImode, REGNO (temp));
1199 	      temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1271 		  temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1673 		  || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
2147   int regno = REGNO (reg);
2601       || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
2607   if (REGNO (SET_DEST (pat)) >= 32)
2649       || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
2650       || REGNO (SET_DEST (pat)) >= 32)
2683       if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2998       if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
2999 	  || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3004       if ((REGNO (rs1) >= 32
3005 	   && REGNO (rs1) != FRAME_POINTER_REGNUM
3006 	   && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3008 	      && (REGNO (rs2) >= 32
3009 		  && REGNO (rs2) != FRAME_POINTER_REGNUM
3010 		  && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3348   const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3449       int regno = REGNO (base);
5006    REGNO is the hard register the union will be passed in.  */
5044    REGNO is the FP hard register the vector will be passed in.  */
5962 	  v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
5966 	      gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG);
6398       if (REGNO (*where) >= 8 && REGNO (*where) < 24)      /* oX or lX */
6400       if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6401 	*where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6420 	  && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6429 	  && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6498   if ((REGNO (reg) % 2) == 0
6517   if (REGNO (x) == REGNO (y))
6522 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6534   if (REGNO (reg1) % 2 != 0)
6538   if (TARGET_V9 && REGNO (reg1) < 32)
6541   return (REGNO (reg1) == REGNO (reg2) - 1);
6601           reg1 = REGNO (XEXP (addr1, 0));
6612       reg1 = REGNO (addr1);
6625   if (reg1 != REGNO (XEXP (addr2, 0)))
6628   if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6656   if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6657     return (REGNO (reg) % 2 == 0);
6733       else if (REGNO (x) < 8)
6734 	fputs (reg_names[REGNO (x)], file);
6735       else if (REGNO (x) >= 24 && REGNO (x) < 32)
6736 	fputs (reg_names[REGNO (x)-16], file);
6743 	fputs (reg_names[REGNO (x)+1], file);
6745 	fputs (reg_names[REGNO (x)], file);
6750 	fputs (reg_names[REGNO (x)], file);
6752 	fputs (reg_names[REGNO (x)+1], file);
6757       fputs (reg_names[REGNO (x)+1], file);
6762       fputs (reg_names[REGNO (x)+2], file);
6767       fputs (reg_names[REGNO (x)+3], file);
6771       if (REGNO (x) == SPARC_ICC_REG)
6784 	fputs (reg_names[REGNO (x)], file);
6928     fputs (reg_names[REGNO (x)], file);
7640     y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
7643       && REG_N_SETS (REGNO (y)) == 1)
8276 	      && (REGNO (op) < FIRST_PSEUDO_REGISTER
8277 		  || reg_renumber[REGNO (op)] >= 0)))
8308 		       && REGNO (op) >= FIRST_PSEUDO_REGISTER
8309 		       && reg_renumber [REGNO (op)] < 0);