config/mips/mips.c

3317   rtx cmp_result;
3321   cmp_result = gen_reg_rtx (CCV2mode);
3322   emit_insn (gen_scc_ps (cmp_result,
3326 					 cmp_result));
3329 					 cmp_result));
10756   rtx cmp_result, op0, op1;
10758   cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10761   emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10775   emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10817   rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10824   cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10831       emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10835       emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10849       condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10856       condition = gen_single_cc (cmp_result, offset);
10861       condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10873   rtx condition, cmp_result;
10879   cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10886   condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));