binutils/opcodes/ppc-opc.c

1413 #define XRA_MASK (X_MASK | RA_MASK)
1415 /* An XRA_MASK with the W field clear.  */
1416 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
3245 { "mtsrdin", X(31,114),	XRA_MASK,	PPC64,		{ RS, RB } },
3397 { "mtsrin",  X(31,242),	XRA_MASK,	PPC32,		{ RS, RB } },
3398 { "mtsri",   X(31,242),	XRA_MASK,	POWER32,	{ RS, RB } },
3733 { "slbmte",  X(31,402), XRA_MASK,	PPC64,		{ RS, RB } },
4084 { "mffgpr",  XRC(31,607,0), XRA_MASK,	POWER6,		{ FRT, RB } },
4094 { "mfsrin",  X(31,659), XRA_MASK,	PPC32,		{ RT, RB } },
4136 { "mftgpr",  XRC(31,735,0), XRA_MASK,	POWER6,		{ RT, FRB } },
4181 { "slbmfev", X(31,851), XRA_MASK,	PPC64,		{ RT, RB } },
4197 { "slbmfee", X(31,915), XRA_MASK,	PPC64,		{ RT, RB } },
4510 { "frsp",    XRC(63,12,0), XRA_MASK,	COM,		{ FRT, FRB } },
4511 { "frsp.",   XRC(63,12,1), XRA_MASK,	COM,		{ FRT, FRB } },
4513 { "fctiw",   XRC(63,14,0), XRA_MASK,	PPCCOM,		{ FRT, FRB } },
4514 { "fcir",    XRC(63,14,0), XRA_MASK,	POWER2,		{ FRT, FRB } },
4515 { "fctiw.",  XRC(63,14,1), XRA_MASK,	PPCCOM,		{ FRT, FRB } },
4516 { "fcir.",   XRC(63,14,1), XRA_MASK,	POWER2,		{ FRT, FRB } },
4518 { "fctiwz",  XRC(63,15,0), XRA_MASK,	PPCCOM,		{ FRT, FRB } },
4519 { "fcirz",   XRC(63,15,0), XRA_MASK,	POWER2,		{ FRT, FRB } },
4520 { "fctiwz.", XRC(63,15,1), XRA_MASK,	PPCCOM,		{ FRT, FRB } },
4521 { "fcirz.",  XRC(63,15,1), XRA_MASK,	POWER2,		{ FRT, FRB } },
4586 { "fneg",    XRC(63,40,0), XRA_MASK,	COM,		{ FRT, FRB } },
4587 { "fneg.",   XRC(63,40,1), XRA_MASK,	COM,		{ FRT, FRB } },
4600 { "fmr",     XRC(63,72,0), XRA_MASK,	COM,		{ FRT, FRB } },
4601 { "fmr.",    XRC(63,72,1), XRA_MASK,	COM,		{ FRT, FRB } },
4614 { "fnabs",   XRC(63,136,0), XRA_MASK,	COM,		{ FRT, FRB } },
4615 { "fnabs.",  XRC(63,136,1), XRA_MASK,	COM,		{ FRT, FRB } },
4627 { "fabs",    XRC(63,264,0), XRA_MASK,	COM,		{ FRT, FRB } },
4628 { "fabs.",   XRC(63,264,1), XRA_MASK,	COM,		{ FRT, FRB } },
4639 { "frin",    XRC(63,392,0), XRA_MASK,	POWER5,		{ FRT, FRB } },
4640 { "frin.",   XRC(63,392,1), XRA_MASK,	POWER5,		{ FRT, FRB } },
4641 { "friz",    XRC(63,424,0), XRA_MASK,	POWER5,		{ FRT, FRB } },
4642 { "friz.",   XRC(63,424,1), XRA_MASK,	POWER5,		{ FRT, FRB } },
4643 { "frip",    XRC(63,456,0), XRA_MASK,	POWER5,		{ FRT, FRB } },
4644 { "frip.",   XRC(63,456,1), XRA_MASK,	POWER5,		{ FRT, FRB } },
4645 { "frim",    XRC(63,488,0), XRA_MASK,	POWER5,		{ FRT, FRB } },
4646 { "frim.",   XRC(63,488,1), XRA_MASK,	POWER5,		{ FRT, FRB } },
4670 { "fctid",   XRC(63,814,0), XRA_MASK,	PPC64,		{ FRT, FRB } },
4671 { "fctid.",  XRC(63,814,1), XRA_MASK,	PPC64,		{ FRT, FRB } },
4673 { "fctidz",  XRC(63,815,0), XRA_MASK,	PPC64,		{ FRT, FRB } },
4674 { "fctidz.", XRC(63,815,1), XRA_MASK,	PPC64,		{ FRT, FRB } },
4679 { "fcfid",   XRC(63,846,0), XRA_MASK,	PPC64,		{ FRT, FRB } },
4680 { "fcfid.",  XRC(63,846,1), XRA_MASK,	PPC64,		{ FRT, FRB } },