binutils/opcodes/alpha-opc.c

225 #define ZA		(FC + 1)
227 #define ZB		(ZA + 1)
416 #define ARG_FPZ1		{ ZA, FB, DFC1 }
421 #define ARG_OPRZ1		{ ZA, RB, DRC1 }
422 #define ARG_OPRLZ1		{ ZA, LIT, RC }
495 			MEM_MASK, BASE, { ZA } },		/* pseudo */
567   { "nop",		OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
568   { "clr",		OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
569   { "mov",		OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
571   { "mov",		OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
1024   { "fnop",		FP(0x17,0x020), BASE, { ZA, ZB, ZC } },	/* pseudo */
1025   { "fclr",		FP(0x17,0x020), BASE, { ZA, ZB, FC } },	/* pseudo */
1049   { "fetch",		MFC(0x18,0x8000), BASE, { ZA, PRB } },
1050   { "fetch_m",		MFC(0x18,0xA000), BASE, { ZA, PRB } },
1054   { "ecb",		MFC(0x18,0xE800), BASE, { ZA, PRB } },	/* ev56 una */
1056   { "wh64",		MFC(0x18,0xF800), BASE, { ZA, PRB } },	/* ev56 una */
1057   { "wh64en",		MFC(0x18,0xFC00), BASE, { ZA, PRB } },	/* ev7 una */
1072 			BASE, { ZA, CPRB } },
1320   { "hw_mtpr",		OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1332   { "hw_jmp", 		EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1333   { "hw_jsr", 		EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1334   { "hw_ret", 		EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1335   { "hw_jcr", 		EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1336   { "hw_coroutine",	EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1337   { "hw_jmp/stall",	EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1338   { "hw_jsr/stall", 	EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1339   { "hw_ret/stall",	EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1340   { "hw_jcr/stall", 	EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1341   { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1483   { "br",		BRA(0x30), BASE, { ZA, BDISP } },	/* pseudo */