Lines Matching refs:val
48 spr_tcp_state(val("t_state")),
49 val("t_state"),
50 spr_ip_version(val("ip_version")),
51 val("lock_tid"),
52 val("rss_fw")
55 val("l2t_ix"),
56 val("smac_sel"),
57 val("tos")
60 val("t_maxseg"), val("recv_scale"),
61 val("recv_tstmp"), val("recv_sack"));
66 val("timer"), val("dack_timer"));
68 val("mod_schd_tx"),
69 val("mod_schd_rx"),
70 ((val("mod_schd_reason2")<<2) | (val("mod_schd_reason1")<<1) |
71 val("mod_schd_reason0"))
76 val("max_rt"), val("t_rxtshift"),
77 val("keepalive"));
79 val("timestamp_offset"),val("timestamp"));
83 val("t_rtt_ts_recent_age"), val("t_rtseq_recent"));
85 val("t_srtt"),val("t_rttvar"));
94 val("snd_una"),val("snd_nxt"),
95 val("snd_max"),val("tx_max"));
97 val("core_fin"), SEQ_SUB(val("tx_max"),val("snd_una"))
99 if (val("recv_scale") && !val("active_open")) {
101 val("rcv_adv"), val("rcv_scale"),
102 val("rcv_adv") << val("rcv_scale"),
103 val("recv_scale"), val("rcv_scale"), val("active_open"));
106 val("rcv_adv"), val("rcv_scale"),
107 val("recv_scale"), val("active_open"));
111 val("snd_cwnd") , val("snd_ssthresh"), val("snd_rec")
118 spr_cctrl_sel(val("cctrl_sel0"),val("cctrl_sel1")),
119 val("cctrl_ecn"), val("cctrl_ece"), val("cctrl_cwr"),
120 val("cctrl_rfr"));
122 val("t_dupacks"), val("dupack_count_odd"),val("fast_recovery"));
124 val("core_more"),val("core_urg"),val("core_push"));
125 PR(" core_flush %u\n",val("core_flush"));
127 val("nagle"), val("ssws_disabled"), val("turbo"));
128 PR(" tx_pdu_out %u\n",val("tx_pdu_out"));
130 val("tx_pace_auto"),val("tx_pace_fixed"),val("tx_queue"));
133 PR(" tx_quiesce %u\n",val("tx_quiesce"));
135 val("tx_channel"),
136 (val("tx_channel")>>1)&1,
137 val("tx_channel")&1
144 val("tx_hdr_ptr"),val("tx_last_ptr"),val("tx_compact"));
151 val("ts_last_ack_sent"),val("rx_compact"));
153 val("rcv_nxt"), val("rx_hdr_offset"));
155 val("rx_frag0_start_idx"),
156 val("rx_frag0_len"),
157 val("rx_ptr"));
159 val("rx_frag1_start_idx_offset"),
160 val("rx_frag1_len"));
165 if (val("ulp_type")!=4) { /* RDMA has FRAG1 idx && len, but no ptr? Should I not display frag1 at all? */
166 PR("frag1_ptr 0x%-8x\n",val("rx_frag1_ptr"));
172 if (val("ulp_type") !=6 && val("ulp_type") != 5 && val("ulp_type") !=4) {
174 val("rx_frag2_start_idx_offset"),
175 val("rx_frag2_len"),
176 val("rx_frag2_ptr"));
178 val("rx_frag3_start_idx_offset"),
179 val("rx_frag3_len"),
180 val("rx_frag3_ptr"));
189 val("peer_fin"),val("rx_pdu_out"), val("pdu_len"));
194 if (val("recv_scale")) {
196 val("rcv_wnd"), val("snd_scale"),
197 val("rcv_wnd") >> val("snd_scale"),
198 val("recv_scale"));
201 val("rcv_wnd"), val("snd_scale"),
202 val("recv_scale"));
209 val("dack_mss"),val("dack"),val("dack_not_acked"));
211 val("rcv_coalesce_enable"),
212 val("rcv_coalesce_push"),
213 val("rcv_coalesce_last_psh"),
214 val("rcv_coalesce_heartbeat"));
217 val("rx_channel"), val("rx_quiesce"),
218 val("rx_flow_control_disable"));
220 val("rx_flow_control_ddp"));
225 ((val("pend_ctl2")<<2) | (val("pend_ctl1")<<1) |
226 val("pend_ctl0")),
227 val("unused"),val("main_slush"));
229 val("migrating"),
230 val("ask_mode"), val("non_offload"), val("rss_info"));
232 val("ulp_type"), spr_ulp_type(val("ulp_type")),
233 val("ulp_raw"));
237 PR(", ulp_ext %u",val("ulp_ext"));
245 val("rdma_error"), val("rdma_flm_error"));
255 val("aux1_slush0"), val("aux1_slush1"));
256 PR(" pdu_hdr_len %u\n",val("pdu_hdr_len"));
268 val("qp_id"), val("pd_id"),val("stag"));
270 val("irs_ulp"),val("iss_ulp"));
272 val("tx_pdu_len"));
274 val("cq_idx_sq"),val("cq_idx_rq"));
276 val("rq_start"),val("rq_msn"),val("rq_max_offset"),
277 val("rq_write_ptr"));
279 val("ord_l_bit_vld"),val("rdmap_opcode"));
281 val("tx_flush"),val("tx_oos_rxmt"),val("tx_oos_txmt"));
294 val("aux3_slush"),val("ddp_buf0_unused"),val("ddp_buf1_unused"),
295 val("ddp_main_unused"));
303 val("ddp_off"),val("ddp_active_buf"),val("ddp_indicate_out"),
304 val("ddp_wait_frag"),val("ddp_rx2tx"),val("ddp_buf_inf")
313 val("ddp_buf0_indicate"),
314 val("ddp_pshf_enable_0"), val("ddp_push_disable_0"),
315 val("ddp_buf0_flush"), val("ddp_psh_no_invalidate0")
318 val("ddp_buf1_indicate"),
319 val("ddp_pshf_enable_1"), val("ddp_push_disable_1"),
320 val("ddp_buf1_flush"), val("ddp_psh_no_invalidate1")
334 val("ddp_buf0_valid"),val("rx_ddp_buf0_offset"),
335 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_tag")
339 if (0==val("ddp_off") && 1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
347 val("ddp_buf1_valid"),val("rx_ddp_buf1_offset"),
348 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_tag")
354 if (0==val("ddp_off") && 1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
365 if (1==val("ddp_off")) {
367 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_active_buf")) {
370 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
371 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
373 if (1==val("ddp_buf1_valid")) {
375 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
376 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
379 } else if (1==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
382 val("rx_ddp_buf1_len"),val("rx_ddp_buf1_offset"),
383 val("rx_ddp_buf1_len")-val("rx_ddp_buf1_offset")
385 if (1==val("ddp_buf0_valid")) {
387 val("rx_ddp_buf0_len"),val("rx_ddp_buf0_offset"),
388 val("rx_ddp_buf0_len")-val("rx_ddp_buf0_offset")
391 } else if (0==val("ddp_buf0_valid") && 1==val("ddp_buf1_valid") && 0==val("ddp_active_buf")) {
393 } else if (1==val("ddp_buf0_valid") && 0==val("ddp_buf1_valid") && 1==val("ddp_active_buf")) {
401 if (0==val("ddp_indicate_out")) {
402 if (0==val("ddp_buf0_indicate") && 0==val("ddp_buf1_indicate")) {
404 if (0==val("rx_hdr_offset")) {
408 val("rx_hdr_offset"));
413 } else if (1==val("ddp_indicate_out")) {
415 if (0==val("rx_hdr_offset")) {
419 val("rx_hdr_offset"));