x86/iommu/intel_drv.c

232 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
236 	dmd = &unit->intrs[idx];
248 dmar_release_resources(device_t dev, struct dmar_unit *unit)
252 	dmar_fini_busdma(unit);
253 	dmar_fini_irt(unit);
254 	dmar_fini_qi(unit);
255 	dmar_fini_fault_log(unit);
257 		dmar_release_intr(dev, unit, i);
258 	if (unit->regs != NULL) {
259 		bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
260 		    unit->regs);
261 		bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
262 		    unit->regs);
263 		unit->regs = NULL;
265 	if (unit->domids != NULL) {
266 		delete_unrhdr(unit->domids);
267 		unit->domids = NULL;
269 	if (unit->ctx_obj != NULL) {
270 		vm_object_deallocate(unit->ctx_obj);
271 		unit->ctx_obj = NULL;
276 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
284 	dmd = &unit->intrs[idx];
308 	    dmd->handler, NULL, unit, &dmd->intr_handle);
321 	dmar_write4(unit, dmd->msi_data_reg, msi_data);
322 	dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
324 	dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
344 	struct dmar_unit *unit;
350 	unit = device_get_softc(dev);
352 		dmd = &unit->intrs[i];
359 			DMAR_LOCK(unit);
360 			(dmd->disable_intr)(unit);
361 			dmar_write4(unit, dmd->msi_data_reg, msi_data);
362 			dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
363 			dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
364 			(dmd->enable_intr)(unit);
365 			DMAR_UNLOCK(unit);
374 dmar_print_caps(device_t dev, struct dmar_unit *unit,
380 	    (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
381 	    DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
383 	caphi = unit->hw_cap >> 32;
384 	device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
388 	    DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
389 	    DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
390 	    DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
391 	if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
392 		printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
394 	ecaphi = unit->hw_ecap >> 32;
395 	device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
399 	printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
400 	    DMAR_ECAP_IRO(unit->hw_ecap));
406 	struct dmar_unit *unit;
411 	unit = device_get_softc(dev);
412 	unit->dev = dev;
413 	unit->unit = device_get_unit(dev);
414 	dmaru = dmar_find_by_index(unit->unit);
417 	unit->segment = dmaru->Segment;
418 	unit->base = dmaru->Address;
419 	unit->reg_rid = DMAR_REG_RID;
420 	unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
421 	    &unit->reg_rid, RF_ACTIVE);
422 	if (unit->regs == NULL) {
426 	unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
427 	unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
428 	unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
430 		dmar_print_caps(dev, unit, dmaru);
431 	dmar_quirks_post_ident(unit);
438 		unit->intrs[i].irq = -1;
440 	unit->intrs[DMAR_INTR_FAULT].name = "fault";
441 	unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
442 	unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
443 	unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
444 	unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
445 	unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
446 	unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
447 	unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
448 	error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
450 		dmar_release_resources(dev, unit);
453 	if (DMAR_HAS_QI(unit)) {
454 		unit->intrs[DMAR_INTR_QI].name = "qi";
455 		unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
456 		unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
457 		unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
458 		unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
459 		unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
460 		unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
461 		unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
462 		error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
464 			dmar_release_resources(dev, unit);
469 	mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
470 	unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
471 	    &unit->lock);
472 	LIST_INIT(&unit->domains);
481 	if ((unit->hw_cap & DMAR_CAP_CM) != 0)
482 		alloc_unr_specific(unit->domids, 0);
484 	unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
492 	dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
493 	DMAR_LOCK(unit);
494 	error = dmar_load_root_entry_ptr(unit);
496 		DMAR_UNLOCK(unit);
497 		dmar_release_resources(dev, unit);
500 	error = dmar_inv_ctx_glob(unit);
502 		DMAR_UNLOCK(unit);
503 		dmar_release_resources(dev, unit);
506 	if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
507 		error = dmar_inv_iotlb_glob(unit);
509 			DMAR_UNLOCK(unit);
510 			dmar_release_resources(dev, unit);
515 	DMAR_UNLOCK(unit);
516 	error = dmar_init_fault_log(unit);
518 		dmar_release_resources(dev, unit);
521 	error = dmar_init_qi(unit);
523 		dmar_release_resources(dev, unit);
526 	error = dmar_init_irt(unit);
528 		dmar_release_resources(dev, unit);
531 	error = dmar_init_busdma(unit);
533 		dmar_release_resources(dev, unit);
538 	DMAR_LOCK(unit);
539 	error = dmar_enable_translation(unit);
541 		DMAR_UNLOCK(unit);
542 		dmar_release_resources(dev, unit);
545 	DMAR_UNLOCK(unit);
742 				    dmar_dev))->unit);
760 				    dmar_devs[i]))->unit);
789 	struct dmar_unit *unit;
803 		unit = (struct dmar_unit *)device_get_softc(dmar_dev);
826 					return (unit);
837 				return (unit);
998 		printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit,
1031 				    dev_dmar->unit);
1059 		printf("dmar%d: instantiating RMRR contexts\n", dmar->unit);
1065 		    dmar->unit));
1149 	struct dmar_unit *unit;
1197 		unit = device_get_softc(dmar_devs[i]);
1198 		LIST_FOREACH(domain, &unit->domains, link) {
1200 				if (pci_domain == unit->segment &&
1219 	struct dmar_unit *unit;
1223 	unit = device_get_softc(dmar_devs[idx]);
1224 	db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
1225 	    dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
1227 	    (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1228 	    (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1229 	    dmar_read4(unit, DMAR_GSTS_REG),
1230 	    dmar_read4(unit, DMAR_FSTS_REG),
1231 	    dmar_read4(unit, DMAR_FECTL_REG));
1232 	if (unit->ir_enabled) {
1234 		    unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1237 	    dmar_read4(unit, DMAR_FEDATA_REG),
1238 	    dmar_read4(unit, DMAR_FEADDR_REG),
1239 	    dmar_read4(unit, DMAR_FEUADDR_REG));
1241 	for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1242 		frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1244 		    (uintmax_t)dmar_read8(unit, frir),
1245 		    (uintmax_t)dmar_read8(unit, frir + 8));
1247 	if (DMAR_HAS_QI(unit)) {
1249 		    dmar_read4(unit, DMAR_IEDATA_REG),
1250 		    dmar_read4(unit, DMAR_IEADDR_REG),
1251 		    dmar_read4(unit, DMAR_IEUADDR_REG));
1252 		if (unit->qi_enabled) {
1257 			    (uintmax_t)unit->inv_queue,
1258 			    (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1259 			    (uintmax_t)unit->inv_queue_size,
1260 			    dmar_read4(unit, DMAR_IQH_REG),
1261 			    dmar_read4(unit, DMAR_IQT_REG),
1262 			    unit->inv_queue_avail,
1263 			    dmar_read4(unit, DMAR_ICS_REG),
1264 			    dmar_read4(unit, DMAR_IECTL_REG),
1265 			    unit->inv_waitd_seq_hw,
1266 			    &unit->inv_waitd_seq_hw,
1267 			    (uintmax_t)unit->inv_waitd_seq_hw_phys,
1268 			    unit->inv_waitd_seq,
1269 			    unit->inv_waitd_gen);
1276 		LIST_FOREACH(domain, &unit->domains, link) {