sparc64/sbus/lsi64854.c

128 	uint32_t csr;
188 	csr = L64854_GCSR(sc);
189 	sc->sc_rev = csr & L64854_DEVID;
213 	DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
252 	uint32_t csr;							\
265 		csr = L64854_GCSR(sc);					\
267 			csr |= D_ESC_DRAIN;				\
269 			csr |= L64854_INVALIDATE;			\
271 		L64854_SCSR(sc, csr);					\
282 	uint32_t csr;							\
290 	csr = L64854_GCSR(sc);					\
291 	csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */	\
292 	csr |= L64854_INVALIDATE;	 	/* XXX FAS ? */		\
293 	L64854_SCSR(sc, csr);						\
301 	uint32_t csr;
304 	csr = L64854_GCSR(sc);
306 	DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr));
311 		bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
317 		L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
319 	csr |= L64854_RESET;		/* reset DMA */
320 	L64854_SCSR(sc, csr);
324 	csr = L64854_GCSR(sc);
325 	csr &= ~L64854_RESET;		/* de-assert reset line */
326 	L64854_SCSR(sc, csr);
329 	csr = L64854_GCSR(sc);
330 	csr |= L64854_INT_EN;		/* enable interrupts */
333 			csr |= D_TWO_CYCLE;
335 			csr |= D_FASTER;
342 		csr &= ~L64854_BURST_SIZE;
344 			csr |= L64854_BURST_32;
346 			csr |= L64854_BURST_16;
348 			csr |= L64854_BURST_0;
351 		csr |= D_ESC_AUTODRAIN;	/* Auto-drain */
353 			csr &= ~D_ESC_BURST;
355 			csr |= D_ESC_BURST;
360 	L64854_SCSR(sc, csr);
364 		sc->sc_dmactl = csr;
368 	DPRINTF(LDB_ANY, ("%s: done, csr 0x%x\n", __func__, csr));
397 	uint32_t csr;
447 	csr = L64854_GCSR(sc);
450 		csr |= L64854_WRITE;
452 		csr &= ~L64854_WRITE;
453 	csr |= L64854_INT_EN;
456 		csr |= (D_DSBL_SCSI_DRN | D_EN_DMA);
458 	L64854_SCSR(sc, csr);
479 	uint32_t csr;
481 	csr = L64854_GCSR(sc);
483 	DPRINTF(LDB_SCSI, ("%s: addr 0x%x, csr %b\n", __func__,
484 	    bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, DDMACSR_BITS));
486 	if (csr & (D_ERR_PEND | D_SLAVE_ERR)) {
487 		device_printf(sc->sc_dev, "error: csr=%b\n", csr,
489 		csr &= ~D_EN_DMA;	/* Stop DMA. */
491 		csr |= D_INVALIDATE | D_SLAVE_ERR;
492 		L64854_SCSR(sc, csr);
503 	csr &= ~D_EN_DMA;
504 	L64854_SCSR(sc, csr);
524 	if ((csr & D_WRITE) == 0 &&
570 		bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
596 	uint32_t csr;
599 	csr = L64854_GCSR(sc);
602 	rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
604 	if (csr & (E_ERR_PEND | E_SLAVE_ERR)) {
605 		device_printf(sc->sc_dev, "error: csr=%b\n", csr,
607 		csr &= ~L64854_EN_DMA;	/* Stop DMA. */
609 		csr |= E_INVALIDATE | E_SLAVE_ERR;
610 		L64854_SCSR(sc, csr);
619 		csr |= E_DRAIN;
620 		L64854_SCSR(sc, csr);
656 	uint32_t csr;
684 	csr = L64854_GCSR(sc);
685 	csr &= ~L64854_BURST_SIZE;
687 		csr |= L64854_BURST_32;
689 		csr |= L64854_BURST_16;
691 		csr |= L64854_BURST_0;
692 	csr |= P_EN_DMA | P_INT_EN | P_EN_CNT;
694 	/* This bit is read-only in PP csr register. */
696 		csr |= P_WRITE;
698 		csr &= ~P_WRITE;
700 	L64854_SCSR(sc, csr);
716 	uint32_t csr;
718 	csr = L64854_GCSR(sc);
720 	DPRINTF(LDB_PP, ("%s: addr 0x%x, csr %b\n", __func__,
721 	    bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, PDMACSR_BITS));
723 	if ((csr & (P_ERR_PEND | P_SLAVE_ERR)) != 0) {
725 		device_printf(sc->sc_dev, "error: resid %d csr=%b\n", resid,
726 		    csr, PDMACSR_BITS);
727 		csr &= ~P_EN_DMA;	/* Stop DMA. */
729 		csr |= P_INVALIDATE | P_SLAVE_ERR;
730 		L64854_SCSR(sc, csr);
734 	ret = (csr & P_INT_PEND) != 0;
742 	csr &= ~D_EN_DMA;
743 	L64854_SCSR(sc, csr);
756 		bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?