powerpc/powermac/dbdma.c

50 dbdma_phys_callback(void *chan, bus_dma_segment_t *segs, int nsegs, int error)
52 	dbdma_channel_t *channel = (dbdma_channel_t *)(chan);
60     bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan)
65 	channel = *chan = malloc(sizeof(struct dbdma_channel), M_DBDMA,
93 dbdma_resize_channel(dbdma_channel_t *chan, int newslots)
99 	chan->sc_nslots = newslots;
104 dbdma_free_channel(dbdma_channel_t *chan)
107 	dbdma_stop(chan);
109 	bus_dmamem_free(chan->sc_dmatag, chan->sc_slots, chan->sc_dmamap);
110 	bus_dma_tag_destroy(chan->sc_dmatag);
112 	free(chan, M_DBDMA);
118 dbdma_get_cmd_status(dbdma_channel_t *chan, int slot)
121 	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
127 	return (le16toh(chan->sc_slots[slot].resCount));
131 dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot)
134 	chan->sc_slots[slot].resCount = 0;
138 dbdma_get_residuals(dbdma_channel_t *chan, int slot)
141 	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, BUS_DMASYNC_POSTREAD);
143 	return (le16toh(chan->sc_slots[slot].xferStatus));
147 dbdma_reset(dbdma_channel_t *chan)
150 	dbdma_stop(chan);
151 	dbdma_set_current_cmd(chan, 0);
152 	dbdma_run(chan);
156 dbdma_run(dbdma_channel_t *chan)
165 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
169 dbdma_pause(dbdma_channel_t *chan)
177 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
181 dbdma_wake(dbdma_channel_t *chan)
190 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
194 dbdma_stop(dbdma_channel_t *chan)
201 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
203 	while (dbdma_read_reg(chan, CHAN_STATUS_REG) & DBDMA_STATUS_ACTIVE)
208 dbdma_set_current_cmd(dbdma_channel_t *chan, int slot)
212 	cmd = chan->sc_slots_pa + slot * sizeof(struct dbdma_command);
213 	dbdma_write_reg(chan, CHAN_CMDPTR, cmd);
217 dbdma_get_chan_status(dbdma_channel_t *chan)
221 	status_reg = dbdma_read_reg(chan, CHAN_STATUS_REG);
226 dbdma_get_device_status(dbdma_channel_t *chan)
228 	return (dbdma_get_chan_status(chan) & 0x00ff);
232 dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, uint8_t value)
240 	dbdma_write_reg(chan, CHAN_CONTROL_REG, control_reg);
244 dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
252 	dbdma_write_reg(chan, CHAN_INTR_SELECT, intr_select);
256 dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
264 	dbdma_write_reg(chan, CHAN_BRANCH_SELECT, br_select);
268 dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, uint8_t val)
275 	dbdma_write_reg(chan, CHAN_WAIT_SELECT, wait_select);
279 dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, int stream,
295 		cmd.cmdDep = chan->sc_slots_pa +
312 	chan->sc_slots[slot] = cmd;
316 dbdma_insert_stop(dbdma_channel_t *chan, int slot)
319 	dbdma_insert_command(chan, slot, DBDMA_STOP, 0, 0, 0, DBDMA_NEVER,
324 dbdma_insert_nop(dbdma_channel_t *chan, int slot)
327 	dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
332 dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot)
335 	dbdma_insert_command(chan, slot, DBDMA_NOP, 0, 0, 0, DBDMA_NEVER,
340 dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op)
343 	bus_dmamap_sync(chan->sc_dmatag, chan->sc_dmamap, op);
347 dbdma_save_state(dbdma_channel_t *chan)
350 	chan->sc_saved_regs[0] = dbdma_read_reg(chan, CHAN_CMDPTR);
351 	chan->sc_saved_regs[1] = dbdma_read_reg(chan, CHAN_CMDPTR_HI);
352 	chan->sc_saved_regs[2] = dbdma_read_reg(chan, CHAN_INTR_SELECT);
353 	chan->sc_saved_regs[3] = dbdma_read_reg(chan, CHAN_BRANCH_SELECT);
354 	chan->sc_saved_regs[4] = dbdma_read_reg(chan, CHAN_WAIT_SELECT);
356 	dbdma_stop(chan);
360 dbdma_restore_state(dbdma_channel_t *chan)
363 	dbdma_wake(chan);
364 	dbdma_write_reg(chan, CHAN_CMDPTR, chan->sc_saved_regs[0]);
365 	dbdma_write_reg(chan, CHAN_CMDPTR_HI, chan->sc_saved_regs[1]);
366 	dbdma_write_reg(chan, CHAN_INTR_SELECT, chan->sc_saved_regs[2]);
367 	dbdma_write_reg(chan, CHAN_BRANCH_SELECT, chan->sc_saved_regs[3]);
368 	dbdma_write_reg(chan, CHAN_WAIT_SELECT, chan->sc_saved_regs[4]);
372 dbdma_read_reg(dbdma_channel_t *chan, u_int offset)
375 	return (bus_read_4(chan->sc_regs, chan->sc_off + offset));
379 dbdma_write_reg(dbdma_channel_t *chan, u_int offset, uint32_t val)
382 	bus_write_4(chan->sc_regs, chan->sc_off + offset, val);