powerpc/powermac/atibl.c

73 	struct resource *sc_memr;
150 	sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
152 	if (sc->sc_memr == NULL) {
172 	bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f));
173 	(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
174 	(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
176 	data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
179 	save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
181 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
182 	tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
183 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
193 	bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX,
195 	(void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
196 	(void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
198 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val);
202 	save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
204 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
205 	tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
206 	bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
223 	lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);
227 		disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN);
229 		bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg);
230 		lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL);
232 		bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
234 		bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
245 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
252 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
255 		bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
270 	lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);