powerpc/booke/locore.S

73  *	r3	: metadata pointer
88  *	r3-r27	: scratch registers
97 	mr	%r30, %r3
103 	li	%r3, PSL_DE	/* Keep debug exceptions for CodeWarrior. */
104 	mtmsr	%r3
111 	mfpvr	%r3
112 	rlwinm	%r3, %r3, 16, 16, 31
118 	cmpli	0, 0, %r3, FSL_E500mc
125 	cmpli	0, 0, %r3, FSL_E5500
139 	cmpli	0, 0, %r3, FSL_E500mc
141 	cmpli	0, 0, %r3, FSL_E5500
144 	lis	%r3, HID1_E500_DEFAULT_SET@h
145 	ori	%r3, %r3, HID1_E500_DEFAULT_SET@l
146 	mtspr	SPR_HID1, %r3
150 	li	%r3, 0
160 1:	mflr	%r3
170 	mfmsr	%r3
171 	ori	%r3, %r3, (PSL_IS | PSL_DS)
176 	mtspr	SPR_SRR1, %r3
182 	mr	%r3, %r29
189 	lis	%r3, MAS0_TLBSEL1@h	/* Select TLB1 */
191 	rlwimi	%r3, %r4, 16, 10, 15
192 	mtspr	SPR_MAS0, %r3
195 	li	%r3, (TLB_SIZE_64M << MAS1_TSIZE_SHIFT)@l
196 	oris	%r3, %r3, (MAS1_VALID | MAS1_IPROT)@h
197 	mtspr	SPR_MAS1, %r3		/* note TS was not filled, so it's TS=0 */
200 	lis	%r3, KERNBASE@h
201 	ori	%r3, %r3, KERNBASE@l	/* EPN = KERNBASE */
203 	ori	%r3, %r3, (_TLB_ENTRY_SHARED | MAS2_M)@l /* WIMGE = 0b00100 */
205 	mtspr	SPR_MAS2, %r3
225 	rlwinm	%r3, %r3, 0, 0, 19
226 	add	%r4, %r4, %r3		/* Convert to kernel virtual address */
228 	li	%r3, PSL_DE		/* Note AS=0 */
230 	mtspr   SPR_SRR1, %r3
236 	mr	%r3, %r28
258 	lwz	%r3,0(%r5)	/* _DYNAMIC in %r3 */
259 	add	%r3,%r3,%r5
263 	subf	%r4,%r4,%r3	/* subtract to calculate relocbase */
274 	mr	%r3, %r30
281 	mr	%r1, %r3
282 	li	%r3, 0
283 	stw	%r3, 0(%r1)
316 	mfpvr	%r3
317 	rlwinm	%r3, %r3, 16, 16, 31
323 	cmpli	0, 0, %r3, FSL_E500mc
329 	cmpli	0, 0, %r3, FSL_E5500
338 	li	%r3, BUCSR_BPEN
339 	mtspr	SPR_BUCSR, %r3
343 	li	%r3, 0
350 2:	mflr	%r3
361 	mfmsr	%r3
362 	ori	%r3, %r3, (PSL_IS | PSL_DS)
367 	mtspr	SPR_SRR1, %r3
373 	mr	%r3, %r29
380 	lis	%r3, MAS0_TLBSEL1@h	/* Select TLB1 */
382 	rlwimi	%r3, %r4, 16, 4, 15
383 	mtspr	SPR_MAS0, %r3
386 	li	%r3, (TLB_SIZE_64M << MAS1_TSIZE_SHIFT)@l
387 	oris	%r3, %r3, (MAS1_VALID | MAS1_IPROT)@h
388 	mtspr	SPR_MAS1, %r3		/* note TS was not filled, so it's TS=0 */
391 	lis	%r3, KERNBASE@h
392 	ori	%r3, %r3, KERNBASE@l	/* EPN = KERNBASE */
393 	ori	%r3, %r3, (_TLB_ENTRY_SHARED | MAS2_M)@l /* WIMGE = 0b00100 */
394 	mtspr	SPR_MAS2, %r3
401 4:	mflr	%r3
402 	lwz	%r4, 0(%r3)
403 	lwz	%r5, 4(%r3)
404 	rlwinm	%r3, %r3, 0, 0, 19
406 	lwzx	%r3, %r4, %r3
409 	ori	%r3, %r3, (MAS3_SX | MAS3_SW | MAS3_SR)@l
410 	mtspr	SPR_MAS3, %r3
420 5:	mflr	%r3
421 	rlwinm	%r3, %r3, 0, 0xfff	/* Offset from boot page start */
422 	add	%r3, %r3, %r5		/* Make this virtual address */
423 	addi	%r3, %r3, 32
425 	mtspr	SPR_SRR0, %r3
438 	mr	%r3, %r28
463 	lwz	%r3, 0(%r4)
464 	add	%r3, %r3, %r4
465 	lwz	%r3, 0(%r3)
466 	mtsprg0	%r3
472 	mr	%r1, %r3
484  * r3	TLBSEL
487 	rlwinm	%r3, %r3, 3, (1 << 3)	/* TLBSEL */
488 	ori	%r3, %r3, (1 << 2)	/* INVALL */
489 	tlbivax	0, %r3
498  * expects address to look up in r3, returns entry number in r29
508 	tlbsx	0, %r3
525  * r3		ESEL
530 	rlwimi	%r4, %r3, 16, 10, 15	/* Select our entry */
545  * r3-r5	scratched
549 	lis	%r3, MAS0_TLBSEL1@h	/* Select TLB1 */
550 	rlwimi	%r3, %r29, 16, 10, 15	/* Select our current entry */
551 	mtspr	SPR_MAS0, %r3
561 	lis	%r3, MAS0_TLBSEL1@h	/* Select TLB1 */
563 	rlwimi	%r3, %r28, 16, 10, 15	/* Select temp entry */
564 	mtspr	SPR_MAS0, %r3
574 	mflr	%r3
577 	mtlr	%r3
588  * r3-r5	scratched
591 	mr	%r6, %r3
592 	mfspr	%r3, SPR_TLB1CFG	/* Get number of entries */
593 	andi.	%r3, %r3, TLBCFG_NENTRY_MASK@l
610 	cmpw	%r4, %r3		/* Check if this is the last entry */
679 	mfspr	%r3, SPR_L1CSR0
680 	ori	%r3, %r3, (L1CSR0_DCFI | L1CSR0_DCLFR)@l
683 	mtspr	SPR_L1CSR0, %r3
685 1:	mfspr	%r3, SPR_L1CSR0
686 	andi.	%r3, %r3, L1CSR0_DCFI
692 	mfspr	%r3, SPR_L1CSR0
695 	and	%r3, %r3, %r4
698 	mtspr	SPR_L1CSR0, %r3
704 	mfspr	%r3, SPR_L1CSR0
705 	oris	%r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@h
706 	ori	%r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@l
709 	mtspr	SPR_L1CSR0, %r3
715 	mfspr	%r3, SPR_L1CSR1
716 	ori	%r3, %r3, (L1CSR1_ICFI | L1CSR1_ICLFR)@l
718 	mtspr	SPR_L1CSR1, %r3
720 1:	mfspr	%r3, SPR_L1CSR1
721 	andi.	%r3, %r3, L1CSR1_ICFI
727 	mfspr	%r3, SPR_L1CSR1
730 	and	%r3, %r3, %r4
732 	mtspr	SPR_L1CSR1, %r3
738 	mfspr	%r3, SPR_L1CSR1
739 	oris	%r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@h
740 	ori	%r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@l
742 	mtspr	SPR_L1CSR1, %r3
751 	mfspr	%r3, SPR_L2CSR0
752 	oris	%r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@h
753 	ori	%r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@l
755 	mtspr	SPR_L2CSR0, %r3
757 1:	mfspr   %r3, SPR_L2CSR0
758 	andis.	%r3, %r3, L2CSR0_L2FI@h
763 	mfspr	%r3, SPR_L2CSR0
764 	oris	%r3, %r3, (L2CSR0_L2E | L2CSR0_L2PE)@h
766 	mtspr	SPR_L2CSR0, %r3
774 	mfspr	%r3, SPR_BUCSR
775 	ori	%r3, %r3, BUCSR_BBFI
777 	mtspr	SPR_BUCSR, %r3
779 	ori	%r3, %r3, BUCSR_BPEN
781 	mtspr	SPR_BUCSR, %r3
823 	stw	%r4, 0(%r3)