Lines Matching refs:val
55 uint32_t val;
57 val = rt305x_sysctl_get(r); printf(" " #r "=%#08x\n", val)
59 val = rt305x_sysctl_get(SYSCTL_CHIPID0_3);
61 (val >> 0 ) & 0xff,
62 (val >> 8 ) & 0xff,
63 (val >> 16) & 0xff,
64 (val >> 24) & 0xff);
65 val = rt305x_sysctl_get(SYSCTL_CHIPID4_7);
67 (val >> 0 ) & 0xff,
68 (val >> 8 ) & 0xff,
69 (val >> 16) & 0xff,
70 (val >> 24) & 0xff);
74 if ( val & SYSCTL_SYSCFG_INIC_EE_SDRAM)
76 if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM)
79 ((val & SYSCTL_SYSCFG_GE0_MODE_MASK) >>
81 if ( val & SYSCTL_SYSCFG_BOOT_ADDR_1F00)
83 if ( val & SYSCTL_SYSCFG_BYPASS_PLL)
85 if ( val & SYSCTL_SYSCFG_BIG_ENDIAN)
87 if ( val & SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ)
90 ((val & SYSCTL_SYSCFG_BOOT_FROM_MASK) >>
93 ((val & SYSCTL_SYSCFG_TEST_CODE_MASK) >>
96 ((val & SYSCTL_SYSCFG_SRAM_CS_MODE_MASK) >>
99 (val & SYSCTL_SYSCFG_SDRAM_CLK_DRV)?12:8);
102 printf("\tSDRAM_CLK_SKEW %uns\n", (val >> 30) & 0x03);
105 if ( val & SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2)
107 if ( val & SYSCTL_CLKCFG1_OTG_CLK_EN)
109 if ( val & SYSCTL_CLKCFG1_I2S_CLK_EN)
112 (val & SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT)?
115 ((val & SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK) >>
117 if ( val & SYSCTL_CLKCFG1_PCM_CLK_EN)
121 (val & SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT)?
124 ((val & SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK) >>
219 rt305x_sysctl_set(uint32_t reg, uint32_t val)
222 bus_write_4(sc->mem_res, reg, val);