dev/net/xaui.c

142 	uint32_t val;
144 	val = ((broadcast_en & 0x1) << 10)  |
150 	nlm_write_nae_reg(base, XAUI_MAC_FILTER_CFG(nblock), val);
201 	uint32_t val;
203 	val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
204 	val &= ~(0x1 << 11);	/* clear soft reset */
205 	nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
207 	val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
208 	val &= ~(0x3 << 11);	/* clear soft reset and hard reset */
209 	nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
214 	val = 0x000010A8;
215 	val |= XAUI_CONFIG_LENCHK;
216 	val |= XAUI_CONFIG_GENFCS;
217 	val |= XAUI_CONFIG_PAD_64;
218 	nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), val);
225 	val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
226 	val |= (0x1 << NETIOR_XGMAC_VLAN_DC_POS);
227 	val |= (0x1 << NETIOR_XGMAC_STATS_EN_POS);
229 		val |= (0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
230 		val |= (0x1 << NETIOR_XGMAC_RX_PFC_EN_POS);
231 		val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
233 		val &= ~(0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
234 		val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
236 	nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
239 		val = 0xF1230000; /* PFC mode, offtimer = 0xf123, ontimer = 0 */
241 		val = 0x0000F123; /* link level FC mode, offtimer = 0xf123 */
242 	nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL2(nblock), val);
245 	val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock));
246 	val &= ~(0x1f << 10);
247 	val |= ~(15 << 10);
248 	nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock), val);