mips/mediatek/mtk_soc.c

82 	uint32_t val;
84 	val = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3);
85 	if (val == RT3350_CHIPID0_3)
88 	val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
89 	val >>= RT305X_CPU_CLKSEL_OFF;
90 	val &= RT305X_CPU_CLKSEL_MSK;
92 	return ((val == 0) ? MTK_CPU_CLK_320MHZ : MTK_CPU_CLK_384MHZ);
98 	uint32_t val;
100 	val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
101 	val >>= RT3352_CPU_CLKSEL_OFF;
102 	val &= RT3352_CPU_CLKSEL_MSK;
104 	if (val)
113 	uint32_t val;
115 	val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
116 	val >>= RT3883_CPU_CLKSEL_OFF;
117 	val &= RT3883_CPU_CLKSEL_MSK;
119 	switch (val) {
166 	uint32_t val, mul, div, res;
168 	val = bus_space_read_4(bst, bsh, SYSCTL_MT7620_CPLL_CFG1);
169 	if (val & MT7620_CPU_CLK_AUX0)
172 	val = bus_space_read_4(bst, bsh, SYSCTL_MT7620_CPLL_CFG0);
173 	if (!(val & MT7620_CPLL_SW_CFG))
176 	mul = MT7620_PLL_MULT_RATIO_BASE + ((val >> MT7620_PLL_MULT_RATIO_OFF) &
178 	div = (val >> MT7620_PLL_DIV_RATIO_OFF) & MT7620_PLL_DIV_RATIO_MSK;
193 	uint32_t val, div, res;
195 	val = bus_space_read_4(bst, bsh, SYSCTL_CLKCFG0);
196 	if (val & MT7621_USES_MEMDIV) {
202 		val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
203 		val >>= MT7621_CLKSEL_OFF;
204 		val &= MT7621_CLKSEL_MSK;
206 		if (val >= MT7621_CLKSEL_25MHZ_VAL)
208 		else if (val >= MT7621_CLKSEL_20MHZ_VAL)
213 		val = bus_space_read_4(bst, bsh, SYSCTL_CUR_CLK_STS);
214 		div = (val >> MT7621_CLK_STS_DIV_OFF) & MT7621_CLK_STS_MSK;
215 		val &= MT7621_CLK_STS_MSK;
217 		res = (MT7621_CLK_STS_BASE * val) / div;
226 	uint32_t val;
228 	val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
229 	val >>= MT7628_CPU_CLKSEL_OFF;
230 	val &= MT7628_CPU_CLKSEL_MSK;
232 	if (val)