mips/atheros/ar71xx_spi.c

65 #define	SPI_BARRIER_WRITE(sc)		bus_barrier((sc)->sc_mem_res, 0, 0, 	\
67 #define	SPI_BARRIER_READ(sc)	bus_barrier((sc)->sc_mem_res, 0, 0, 	\
69 #define	SPI_BARRIER_RW(sc)		bus_barrier((sc)->sc_mem_res, 0, 0, 	\
72 #define SPI_WRITE(sc, reg, val)	do {				\
73 		bus_write_4(sc->sc_mem_res, (reg), (val));	\
76 #define SPI_READ(sc, reg)	 bus_read_4(sc->sc_mem_res, (reg))
78 #define SPI_SET_BITS(sc, reg, bits)	\
79 	SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits))
81 #define SPI_CLEAR_BITS(sc, reg, bits)	\
82 	SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits))
100 	struct ar71xx_spi_softc *sc = device_get_softc(dev);
103 	sc->sc_dev = dev;
105 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
107 	if (!sc->sc_mem_res) {
112 	SPI_WRITE(sc, AR71XX_SPI_FS, 1);
115 	SPI_BARRIER_WRITE(sc);
117 	sc->sc_reg_ctrl  = SPI_READ(sc, AR71XX_SPI_CTRL);
122 	SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43);
128 	SPI_BARRIER_WRITE(sc);
129 	SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
134 	SPI_BARRIER_WRITE(sc);
141 ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs)
155 	SPI_BARRIER_WRITE(sc);
156 	SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl);
157 	SPI_BARRIER_WRITE(sc);
161 ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs)
166 	SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK);
170 ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data)
186 		SPI_BARRIER_WRITE(sc);
187 		SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
188 		SPI_BARRIER_WRITE(sc);
189 		SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK);
195 	SPI_BARRIER_WRITE(sc);
196 	SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod);
197 	SPI_BARRIER_WRITE(sc);
198 	rds = SPI_READ(sc, AR71XX_SPI_RDS);
206 	struct ar71xx_spi_softc *sc;
211 	sc = device_get_softc(dev);
217 	ar71xx_spi_chip_activate(sc, cs);
230 		buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]);
238 		buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]);
240 	ar71xx_spi_chip_deactivate(sc, cs);
248 	struct ar71xx_spi_softc *sc = device_get_softc(dev);
254 	SPI_BARRIER_WRITE(sc);
260 	SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl);
261 	SPI_BARRIER_WRITE(sc);
267 	SPI_WRITE(sc, AR71XX_SPI_FS, 0);
268 	SPI_BARRIER_WRITE(sc);
270 	if (sc->sc_mem_res)
271 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);