vxge/vxgehal/vxgehal-vpath-reg.h

43 #define	VXGE_HAL_USDC_VPATH_SGRP_ASSIGN(val)		    vBIT(val, 0, 32)
59 #define	VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(val)		    vBIT(val, 3, 29)
65 #define	VXGE_HAL_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val)	    vBIT(val, 40, 2)
70 #define	VXGE_HAL_PRC_CFG4_RING_MODE(val)		    vBIT(val, 14, 2)
77 #define	VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(val)		    vBIT(val, 40, 24)
79 #define	VXGE_HAL_PRC_CFG5_RXD0_ADD(val)			    vBIT(val, 0, 61)
86 #define	VXGE_HAL_PRC_CFG6_RXD_CRXDT(val)		    vBIT(val, 23, 9)
87 #define	VXGE_HAL_PRC_CFG6_RXD_SPAT(val)			    vBIT(val, 36, 9)
89 #define	VXGE_HAL_PRC_CFG7_SCATTER_MODE(val)		    vBIT(val, 6, 2)
93 #define	VXGE_HAL_PRC_CFG7_RXD_BUFF_SIZE_MASK(val)	    vBIT(val, 20, 4)
94 #define	VXGE_HAL_PRC_CFG7_BUFF_SIZE0_MASK(val)		    vBIT(val, 27, 5)
96 #define	VXGE_HAL_TIM_DEST_ADDR_TIM_DEST_ADDR(val)	    vBIT(val, 0, 64)
98 #define	VXGE_HAL_PRC_RXD_DOORBELL_NEW_QW_CNT(val)	    vBIT(val, 48, 16)
100 #define	VXGE_HAL_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val)	    vBIT(val, 59, 5)
102 #define	VXGE_HAL_RXDMEM_SIZE_PRC_RXDMEM_SIZE(val)	    vBIT(val, 51, 13)
104 #define	VXGE_HAL_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val)\
105 							    vBIT(val, 59, 5)
107 #define	VXGE_HAL_RX_MULTI_CAST_STATS_FRAME_DISCARD(val)	    vBIT(val, 48, 16)
109 #define	VXGE_HAL_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) vBIT(val, 32, 32)
111 #define	VXGE_HAL_RXD_RETURNED_RXD_RETURNED(val)		    vBIT(val, 48, 16)
115 #define	VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(val)	    vBIT(val, 17, 15)
116 #define	VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val)	    vBIT(val, 33, 15)
117 #define	VXGE_HAL_KDFC_FIFO_TRPL_PARTITION_LENGTH_2(val)	    vBIT(val, 49, 15)
121 #define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_MODE(val)	    vBIT(val, 14, 2)
124 #define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL(val)	    vBIT(val, 26, 2)
129 #define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_SELECT(val)	    vBIT(val, 32, 8)
130 #define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_INT_NO(val)	    vBIT(val, 41, 7)
131 #define	VXGE_HAL_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP(val)	    vBIT(val, 48, 16)
133 #define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_MODE(val)	    vBIT(val, 14, 2)
136 #define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL(val)	    vBIT(val, 26, 2)
141 #define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_SELECT(val)	    vBIT(val, 32, 8)
142 #define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_INT_NO(val)	    vBIT(val, 41, 7)
143 #define	VXGE_HAL_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP(val)	    vBIT(val, 48, 16)
147 #define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL(val)	    vBIT(val, 26, 2)
152 #define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_SELECT(val)	    vBIT(val, 32, 8)
153 #define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_INT_NO(val)	    vBIT(val, 41, 7)
154 #define	VXGE_HAL_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP(val)	    vBIT(val, 48, 16)
156 #define	VXGE_HAL_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD(val)	    vBIT(val, 0, 64)
158 #define	VXGE_HAL_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD(val)	    vBIT(val, 0, 64)
160 #define	VXGE_HAL_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD(val)	    vBIT(val, 0, 64)
162 #define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0(val)	    vBIT(val, 1, 15)
163 #define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val)	    vBIT(val, 17, 15)
164 #define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2(val)	    vBIT(val, 33, 15)
166 #define	VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) vBIT(val, 17, 15)
190 #define	VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(val)	    vBIT(val, 2, 14)
192 #define	VXGE_HAL_RXMAC_VCFG0_RTS_MIN_FRM_LEN(val)	    vBIT(val, 26, 14)
198 #define	VXGE_HAL_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(val)  vBIT(val, 42, 2)
202 #define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_ACTION(val)	    vBIT(val, 1, 7)
203 #define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vBIT(val, 8, 4)
207 #define	VXGE_HAL_RTS_ACCESS_STEER_CTRL_OFFSET(val)	    vBIT(val, 40, 8)
210 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_DATA(val)	    vBIT(val, 0, 64)
212 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DATA(val)	    vBIT(val, 0, 64)
216 #define	VXGE_HAL_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(val)	    vBIT(val, 3, 5)
219 #define	VXGE_HAL_XMAC_STATS_ACCESS_CMD_OP(val)		    vBIT(val, 6, 2)
221 #define	VXGE_HAL_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(val)	    vBIT(val, 32, 8)
223 #define	VXGE_HAL_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val)	    vBIT(val, 0, 64)
246 #define	VXGE_HAL_RTDMA_BW_CTRL_DESIRED_BW(val)		    vBIT(val, 46, 18)
249 #define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val)   vBIT(val, 6, 2)
250 #define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vBIT(val, 8, 8)
252 #define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val)\
253 							    vBIT(val, 21, 3)
255 #define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val)\
256 							    vBIT(val, 29, 3)
258 #define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) vBIT(val, 37, 3)
260 #define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH(val)\
261 							    vBIT(val, 51, 5)
263 #define	VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) vBIT(val, 61, 3)
272 #define	VXGE_HAL_TIM_CFG1_INT_NUM_BTIMER_VAL(val)	    vBIT(val, 6, 26)
278 #define	VXGE_HAL_TIM_CFG1_INT_NUM_URNG_A(val)		    vBIT(val, 41, 7)
279 #define	VXGE_HAL_TIM_CFG1_INT_NUM_URNG_B(val)		    vBIT(val, 49, 7)
280 #define	VXGE_HAL_TIM_CFG1_INT_NUM_URNG_C(val)		    vBIT(val, 57, 7)
282 #define	VXGE_HAL_TIM_CFG2_INT_NUM_UEC_A(val)		    vBIT(val, 0, 16)
283 #define	VXGE_HAL_TIM_CFG2_INT_NUM_UEC_B(val)		    vBIT(val, 16, 16)
284 #define	VXGE_HAL_TIM_CFG2_INT_NUM_UEC_C(val)		    vBIT(val, 32, 16)
285 #define	VXGE_HAL_TIM_CFG2_INT_NUM_UEC_D(val)		    vBIT(val, 48, 16)
288 #define	VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(val)	    vBIT(val, 1, 4)
289 #define	VXGE_HAL_TIM_CFG3_INT_NUM_RTIMER_VAL(val)	    vBIT(val, 6, 26)
290 #define	VXGE_HAL_TIM_CFG3_INT_NUM_UTIL_SEL(val)		    vBIT(val, 32, 6)
291 #define	VXGE_HAL_TIM_CFG3_INT_NUM_LTIMER_VAL(val)	    vBIT(val, 38, 26)
293 #define	VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(val)	    vBIT(val, 0, 32)
294 #define	VXGE_HAL_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val)	    vBIT(val, 35, 5)
296 #define	VXGE_HAL_TIM_WRKLD_CLC_CNT_RX_TX(val)		    vBIT(val, 41, 2)
298 #define	VXGE_HAL_TIM_WRKLD_CLC_HOST_UTIL(val)		    vBIT(val, 57, 7)
300 #define	VXGE_HAL_TIM_BITMAP_MASK(val)			    vBIT(val, 0, 32)
304 #define	VXGE_HAL_TIM_RING_ASSN_INT_NUM(val)		    vBIT(val, 6, 2)
309 #define	VXGE_HAL_TIM_REMAP_TO_VPATH_NUM(val)		    vBIT(val, 11, 5)
311 #define	VXGE_HAL_TIM_VPATH_MAP_BMAP_ROOT(val)		    vBIT(val, 0, 32)
320 #define	VXGE_HAL_SGRP_ASSIGN_SGRP_ASSIGN(val)		    vBIT(val, 0, 64)
322 #define	VXGE_HAL_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val)\
323 							    vBIT(val, 0, 64)
352 #define	VXGE_HAL_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT(val)	    vBIT(val, 32, 32)
354 #define	VXGE_HAL_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT(val)\
355 							    vBIT(val, 0, 32)
356 #define	VXGE_HAL_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val)\
357 							    vBIT(val, 32, 32)
359 #define	VXGE_HAL_TXPE_PCI_NCE_CFG_NCE_THRESH(val)	    vBIT(val, 0, 32)
379 #define	VXGE_HAL_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val)	    vBIT(val, 0, 64)
383 #define	VXGE_HAL_DMQ_IR_INT_NUMBER(val)			    vBIT(val, 9, 7)
384 #define	VXGE_HAL_DMQ_IR_INT_BITMAP(val)			    vBIT(val, 16, 16)
386 #define	VXGE_HAL_DMQ_BWR_INIT_ADD_HOST(val)		    vBIT(val, 0, 64)
388 #define	VXGE_HAL_DMQ_BWR_INIT_BYTE_COUNT(val)		    vBIT(val, 0, 32)
390 #define	VXGE_HAL_DMQ_IR_POLICY(val)			    vBIT(val, 0, 8)
394 #define	VXGE_HAL_UMQ_INT_NUMBER(val)			    vBIT(val, 9, 7)
395 #define	VXGE_HAL_UMQ_INT_BITMAP(val)			    vBIT(val, 16, 16)
397 #define	VXGE_HAL_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER(val)	    vBIT(val, 0, 8)
401 #define	VXGE_HAL_UMQ_MR2VP_BWR_EOL_POLL_LATENCY(val)	    vBIT(val, 32, 32)
403 #define	VXGE_HAL_UMQ_BWR_INIT_ADD_HOST(val)		    vBIT(val, 0, 64)
405 #define	VXGE_HAL_UMQ_BWR_INIT_BYTE_COUNT(val)		    vBIT(val, 0, 32)
409 #define	VXGE_HAL_GENDMA_INT_NUMBER(val)			    vBIT(val, 9, 7)
410 #define	VXGE_HAL_GENDMA_INT_BITMAP(val)			    vBIT(val, 16, 16)
427 #define	VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val)\
428 							    vBIT(val, 48, 16)
446 #define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_IP_DATA0_DATA(val) vBIT(val, 0, 64)
448 #define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_IP_DATA1_DATA(val) vBIT(val, 0, 64)
450 #define	VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_VLAN_DATA_VLAN_VID(val)\
451 							    vBIT(val, 0, 12)
455 #define	VXGE_HAL_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val)	    vBIT(val, 0, 16)
456 #define	VXGE_HAL_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val)	    vBIT(val, 16, 16)
457 #define	VXGE_HAL_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val)	    vBIT(val, 32, 16)
459 #define	VXGE_HAL_DBG_STATS_RX_FAU_RX_WOL_FRMS(val)	    vBIT(val, 0, 16)
460 #define	VXGE_HAL_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val)\
461 							    vBIT(val, 16, 16)
462 #define	VXGE_HAL_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val)    vBIT(val, 32, 32)
482 #define	VXGE_HAL_VPATH_TO_SRPCIM_WMSG_WMSG(val)		vBIT(val, 0, 64)
539 #define	VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_PPIF_ALARM(val)  vBIT(val, 0, 17)
545 #define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES(val)	    vBIT(val, 0, 8)
546 #define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val)	    vBIT(val, 8, 8)
547 #define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES(val)	    vBIT(val, 16, 8)
548 #define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR(val)    vBIT(val, 24, 8)
549 #define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR(val)    vBIT(val, 32, 8)
550 #define	VXGE_HAL_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR(val)    vBIT(val, 40, 8)
553 #define	VXGE_HAL_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val)   vBIT(val, 6, 2)
555 #define	VXGE_HAL_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX(val)	    vBIT(val, 0, 12)
557 #define	VXGE_HAL_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX(val)	    vBIT(val, 0, 12)
559 #define	VXGE_HAL_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX(val)	    vBIT(val, 0, 12)
563 #define	VXGE_HAL_TGT_ILLEGAL_ACCESS_SWIF_REGION(val)	    vBIT(val, 1, 7)
567 #define	VXGE_HAL_VPATH_GENERAL_CFG1_TC_VALUE(val)	    vBIT(val, 1, 3)
577 #define	VXGE_HAL_VPATH_GENERAL_CFG2_SIZE_QUANTUM(val)	    vBIT(val, 1, 3)
614 #define	VXGE_HAL_DBLGEN_CFG0_NO_OF_QWORDS(val)		    vBIT(val, 0, 12)
620 #define	VXGE_HAL_DBLGEN_CFG1_FIFO0_BUFFER_START_ADDR(val)   vBIT(val, 0, 64)
622 #define	VXGE_HAL_DBLGEN_CFG2_FIFO1_BUFFER_START_ADDR(val)   vBIT(val, 0, 64)
624 #define	VXGE_HAL_DBLGEN_CFG3_FIFO2_BUFFER_START_ADDR(val)   vBIT(val, 0, 64)
626 #define	VXGE_HAL_DBLGEN_CFG4_TRIPLET_PRIORITY_VP_NUMBER(val) vBIT(val, 3, 5)
628 #define	VXGE_HAL_DBLGEN_CFG5_FIFO0_WRIDX(val)		    vBIT(val, 0, 12)
630 #define	VXGE_HAL_DBLGEN_CFG6_FIFO1_WRIDX(val)		    vBIT(val, 0, 12)
632 #define	VXGE_HAL_DBLGEN_CFG7_FIFO2_WRIDX(val)		    vBIT(val, 0, 12)
634 #define	VXGE_HAL_STATS_CFG_START_HOST_ADDR(val)		    vBIT(val, 0, 57)
636 #define	VXGE_HAL_INTERRUPT_CFG0_MSIX_FOR_RXTI(val)	    vBIT(val, 1, 7)
637 #define	VXGE_HAL_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val)   vBIT(val, 9, 7)
638 #define	VXGE_HAL_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(val)   vBIT(val, 17, 7)
639 #define	VXGE_HAL_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(val)   vBIT(val, 25, 7)
640 #define	VXGE_HAL_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(val)   vBIT(val, 33, 7)
644 #define	VXGE_HAL_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(val)	    vBIT(val, 1, 7)
656 #define	VXGE_HAL_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val)	    vBIT(val, 0, 12)
662 #define	VXGE_HAL_PCI_CONFIG_ACCESS_STATUS_DATA(val)	    vBIT(val, 32, 32)
666 #define	VXGE_HAL_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT(val)   vBIT(val, 0, 32)
668 #define	VXGE_HAL_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT(val)   vBIT(val, 0, 32)
670 #define	VXGE_HAL_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD(val)   vBIT(val, 0, 32)
672 #define	VXGE_HAL_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT(val) vBIT(val, 0, 64)
674 #define	VXGE_HAL_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD(val) vBIT(val, 0, 64)
676 #define	VXGE_HAL_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF(val)	    vBIT(val, 32, 32)
678 #define	VXGE_HAL_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF(val)	    vBIT(val, 32, 32)
680 #define	VXGE_HAL_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1(val)\
681 							    vBIT(val, 0, 32)
682 #define	VXGE_HAL_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val)\
683 							    vBIT(val, 32, 32)
685 #define	VXGE_HAL_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3(val)\
686 							    vBIT(val, 0, 32)
687 #define	VXGE_HAL_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val)\
688 							    vBIT(val, 32, 32)
690 #define	VXGE_HAL_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4(val)\
691 							    vBIT(val, 32, 32)
693 #define	VXGE_HAL_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5(val)\
694 							    vBIT(val, 32, 32)
714 #define	VXGE_HAL_H2L_ZERO_BYTE_READ_ADDRESS_H2L_ZERO_BYTE_READ_ADDRESS(val)\
715 							    vBIT(val, 0, 64)