vxge/vxgehal/vxgehal-regdefs.h

102 #define	VXGE_HAL_TOC_GET_KDFC_INITIAL_OFFSET(val)\
103 					(val&~VXGE_HAL_TOC_KDFC_INITIAL_BIR(7))
104 #define	VXGE_HAL_TOC_GET_KDFC_INITIAL_BIR(val)		    bVAL3(val, 61)
105 #define	VXGE_HAL_TOC_GET_USDC_INITIAL_OFFSET(val)\
106 					(val&~VXGE_HAL_TOC_USDC_INITIAL_BIR(7))
107 #define	VXGE_HAL_TOC_GET_USDC_INITIAL_BIR(val)		    bVAL3(val, 61)
119 #define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val)  vBIT(val, 42, 5)
120 #define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val)   vBIT(val, 47, 2)
121 #define	VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) vBIT(val, 49, 15)
152 #define	VXGE_HAL_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val)	    vBIT(val, 0, 48)
155 #define	VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val)  vBIT(val, 0, 48)
159 #define	VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val)	vBIT(val, 55, 5)
162 #define	VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val)  vBIT(val, 62, 2)
226 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val)    vBIT(val, 0, 48)
229 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(val)	    vBIT(val, 0, 12)
232 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(val)	    vBIT(val, 0, 16)
234 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_TYPE(val)	vBIT(val, 0, 8)
235 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DEST(val)	vBIT(val, 8, 8)
236 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_SRC(val)    vBIT(val, 16, 8)
237 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEND_MSG_DATA(val)    vBIT(val, 32, 32)
244 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM(val)    vBIT(val, 8, 16)
250 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(val) vBIT(val, 4, 4)
253 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(val) vBIT(val, 10, 2)
287 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(val)\
288 							    vBIT(val, 9, 7)
292 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(val)\
293 							    vBIT(val, 0, 8)
299 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(val)\
300 							    vBIT(val, 9, 7)
303 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(val)\
304 							    vBIT(val, 16, 8)
310 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(val)\
311 							    vBIT(val, 25, 7)
314 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(val)\
315 							    vBIT(val, 0, 8)
321 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(val)\
322 							    vBIT(val, 9, 7)
325 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(val)\
326 							    vBIT(val, 16, 8)
332 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(val)\
333 							    vBIT(val, 25, 7)
337 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO(val)\
338 							    vBIT(val, 0, 32)
341 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE(val)\
342 							    vBIT(val, 32, 32)
346 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK(val)\
347 							    vBIT(val, 0, 16)
350 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK(val)\
351 							    vBIT(val, 16, 16)
354 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK(val)\
355 							    vBIT(val, 32, 4)
358 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK(val)\
359 							    vBIT(val, 36, 4)
362 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK(val)	vBIT(val, 40, 2)
365 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK(val)	vBIT(val, 42, 2)
368 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY		vBIT(val, 0, 64)
378 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(val)	vBIT(val, 0, 48)
382 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val)\
383 							    vBIT(val, 55, 5)
386 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(val)	vBIT(val, 62, 2)
390 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM(val)\
391 							    vBIT(val, 0, 8)
397 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA(val)\
398 							    vBIT(val, 9, 7)
401 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM(val)\
402 							    vBIT(val, 16, 8)
408 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA(val)\
409 							    vBIT(val, 25, 7)
412 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM(val)\
413 							    vBIT(val, 32, 8)
419 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA(val)\
420 							    vBIT(val, 41, 7)
423 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM(val)\
424 							    vBIT(val, 48, 8)
430 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA(val)\
431 							    vBIT(val, 57, 7)
459 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_STATUS(val)		\
460 							    vBIT(val, 56, 8)
466 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_MEMO_ITEM_LAG_MODE(val)		\
467 							    vBIT(val, 61, 3)
476 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_ADDR(val)	    vBIT(val, 16, 16)
480 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_BYTE_COUNT(val)	    vBIT(val, 40, 8)
483 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_VH(val)		    vBIT(val, 48, 8)
485 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNCTION(val)	    vBIT(val, 56, 8)
488 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_PCI_DATA(val)	    vBIT(val, 32, 32)
491 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_PCI_DATA(val)	    vBIT(val, 32, 32)
497 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE(val)	    vBIT(val, 1, 7)
507 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DEST(val)	    vBIT(val, 8, 8)
511 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_SRC(val)	    vBIT(val, 16, 8)
513 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SEQ_NUM(val)	    vBIT(val, 32, 16)
515 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_DATA(val)	    vBIT(val, 48, 16)
522 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_VHN(val)		vBIT(val, 48, 8)
523 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_VFID(val)		vBIT(val, 56, 8)
529 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_PRIORITY(val)	vBIT(val, 45, 3)
530 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MIN_BW(val)	vBIT(val, 48, 8)
531 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_RX_MAX_BW(val)	vBIT(val, 56, 8)
532 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_VPATH_OR_FUNC(val)	vBIT(val, 0, 8)
538 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_PRIORITY(val)	vBIT(val, 21, 3)
539 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MIN_BW(val)	vBIT(val, 24, 8)
540 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA1_SET_TX_MAX_BW(val)	vBIT(val, 32, 8)
544 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE(val)		vBIT(val, 56, 8)
560 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_DAY(val)	vBIT(val, 0, 8)
563 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH(val)   vBIT(val, 8, 8)
565 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR(val)    vBIT(val, 16, 16)
569 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR	vBIT(val, 32, 8)
572 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR	vBIT(val, 40, 8)
575 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD	vBIT(val, 48, 16)
579 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_DAY(val)  vBIT(val, 0, 8)
582 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MONTH(val) vBIT(val, 8, 8)
585 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_YEAR(val) vBIT(val, 16, 16)
589 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MAJOR	    vBIT(val, 32, 8)
592 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_MINOR	    vBIT(val, 40, 8)
595 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_FLASH_VER_BUILD	    vBIT(val, 48, 16)
598 #define	VXGE_HAL_RTS_ACCESS_STEER_DATA0_SET_NWIF_CMD(val)	vBIT(val, 0, 8)
667 #define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_ADDR(val)	(val<<8)
671 #define	VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_DATA(val)\
672 							    (val&0xff)
719 #define	VXGE_HAL_MDIO_GEN_CFG_PORT_MDIO_PHY_PRTAD(val)	    vBIT(val, 19, 5)
722 #define	VXGE_HAL_XGXS_STATIC_CFG_PORT_MDIO_DTE_PRTAD(val)   vBIT(val, 7, 5)