dev/vnic/nicvf_queues.c

130 	uint64_t reg_val;
137 		reg_val = nicvf_queue_reg_read(nic, reg, qidx);
138 		if (((reg_val & bit_mask) >> bit_pos) == val)
2046 	uint64_t reg_val;
2048 	reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S);
2052 		reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT);
2055 		reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT);
2058 		reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT);
2061 		reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT);
2064 		reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT);
2067 		reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT);
2070 		reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT);
2078 	nicvf_reg_write(nic, NIC_VF_ENA_W1S, reg_val);
2085 	uint64_t reg_val = 0;
2089 		reg_val |= ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT);
2092 		reg_val |= ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT);
2095 		reg_val |= ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT);
2098 		reg_val |= (1UL << NICVF_INTR_PKT_DROP_SHIFT);
2101 		reg_val |= (1UL << NICVF_INTR_TCP_TIMER_SHIFT);
2104 		reg_val |= (1UL << NICVF_INTR_MBOX_SHIFT);
2107 		reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT);
2115 	nicvf_reg_write(nic, NIC_VF_ENA_W1C, reg_val);
2122 	uint64_t reg_val = 0;
2126 		reg_val = ((1UL << q_idx) << NICVF_INTR_CQ_SHIFT);
2129 		reg_val = ((1UL << q_idx) << NICVF_INTR_SQ_SHIFT);
2132 		reg_val = ((1UL << q_idx) << NICVF_INTR_RBDR_SHIFT);
2135 		reg_val = (1UL << NICVF_INTR_PKT_DROP_SHIFT);
2138 		reg_val = (1UL << NICVF_INTR_TCP_TIMER_SHIFT);
2141 		reg_val = (1UL << NICVF_INTR_MBOX_SHIFT);
2144 		reg_val |= (1UL << NICVF_INTR_QS_ERR_SHIFT);
2152 	nicvf_reg_write(nic, NIC_VF_INT, reg_val);
2159 	uint64_t reg_val;
2162 	reg_val = nicvf_reg_read(nic, NIC_VF_ENA_W1S);
2192 	return (reg_val & mask);