Lines Matching refs:temp
176 uint32_t temp;
179 temp = count & ~3;
182 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
186 count -= temp;
193 if (buf_res.length > temp)
194 buf_res.length = temp;
202 temp -= buf_res.length;
203 } while (temp != 0);
226 uint32_t temp;
229 temp = count & ~3;
232 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
236 count -= temp;
243 if (buf_res.length > temp)
244 buf_res.length = temp;
253 temp -= buf_res.length;
254 } while (temp != 0);
279 uint32_t temp;
285 for (temp = 0; temp != 16; temp++) {
479 uint32_t temp;
482 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK;
483 if (temp >= 10000)
484 temp /= 1000;
486 temp /= 125;
489 if (temp >= 54)
490 temp = 60; /* MHz */
491 else if (temp >= 39)
492 temp = 48; /* MHz */
494 temp = 30; /* MHz */
497 temp *= 125;
499 temp *= 1000;
501 DPRINTF("HFIR=0x%08x\n", temp);
503 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp);
537 uint32_t temp;
545 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
546 temp &= ~DCTL_SFTDISCON;
547 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
554 uint32_t temp;
561 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
562 temp |= DCTL_SFTDISCON;
563 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
637 uint32_t temp;
640 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
641 temp |= DCTL_RMTWKUPSIG;
642 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
647 temp &= ~DCTL_RMTWKUPSIG;
648 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
678 uint32_t temp;
682 temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
683 temp &= ~DCFG_DEVADDR_SET(0x7F);
684 temp |= DCFG_DEVADDR_SET(addr);
685 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
725 uint32_t temp;
727 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
735 if (!(temp & GINTSTS_PTXFEMP)) {
744 if (!(temp & GINTSTS_NPTXFEMP)) {
1105 uint32_t temp;
1188 temp = sc->sc_out_ctl[0];
1192 temp | DOEPCTL_STALL);
1194 temp = sc->sc_in_ctl[0];
1198 temp | DIEPCTL_STALL);
1671 uint32_t temp;
1748 temp = sc->sc_out_ctl[td->ep_no];
1751 if ((temp & DIEPCTL_EPTYPE_MASK) ==
1754 if (temp & DIEPCTL_SETD1PID) {
1755 temp &= ~DIEPCTL_SETD1PID;
1756 temp |= DIEPCTL_SETD0PID;
1758 temp &= ~DIEPCTL_SETD0PID;
1759 temp |= DIEPCTL_SETD1PID;
1761 sc->sc_out_ctl[td->ep_no] = temp;
1789 temp = sc->sc_out_ctl[td->ep_no];
1790 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
2142 uint32_t temp;
2152 temp = sc->sc_last_rx_status;
2154 if ((td->ep_no == 0) && (temp != 0) &&
2155 (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2157 if ((temp & GRXSTSRD_PKTSTS_MASK) !=
2159 (temp & GRXSTSRD_PKTSTS_MASK) !=
2180 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2183 cpkt = DXEPTSIZ_GET_NPKT(temp);
2229 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2231 if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2235 DXEPTSIZ_GET_NPKT(temp),
2236 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2293 temp = sc->sc_in_ctl[td->ep_no];
2296 if ((temp & DIEPCTL_EPTYPE_MASK) ==
2299 if (temp & DIEPCTL_SETD1PID) {
2300 temp &= ~DIEPCTL_SETD1PID;
2301 temp |= DIEPCTL_SETD0PID;
2303 temp &= ~DIEPCTL_SETD0PID;
2304 temp |= DIEPCTL_SETD1PID;
2306 sc->sc_in_ctl[td->ep_no] = temp;
2310 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2332 uint32_t temp;
2337 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2340 if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2350 temp = sc->sc_last_rx_status;
2352 if ((td->ep_no == 0) && (temp != 0) &&
2353 (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2355 if ((temp & GRXSTSRD_PKTSTS_MASK) ==
2357 (temp & GRXSTSRD_PKTSTS_MASK) ==
2509 uint16_t temp;
2512 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK;
2514 if (sc->sc_last_frame_num == temp)
2517 sc->sc_last_frame_num = temp;
2521 if ((temp & 7) == 0) {
2551 td->tt_start_slot = temp + slot;
2572 td->tt_start_slot = temp;
2598 td->tt_start_slot = temp;
2618 td->tt_start_slot = temp;
2624 if ((temp & 7) < 6) {
2638 td->tt_start_slot = temp;
2669 if ((temp & 7) == 0) {
2672 (int)temp, (int)sc->sc_needsof);
2698 uint32_t temp;
2724 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
2725 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp);
2726 temp &= ~HCINT_SOFTWARE_ONLY;
2727 sc->sc_chan_state[x].hcint |= temp;
2733 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2734 if (temp & GINTSTS_RXFLVL) {
2744 temp = sc->sc_last_rx_status &
2748 if (temp != GRXSTSRD_STP_DATA &&
2749 temp != GRXSTSRD_STP_COMPLETE &&
2750 temp != GRXSTSRD_OUT_DATA) {
2752 if (temp == GRXSTSRH_HALTED) {
2766 temp = GRXSTSRD_BCNT_GET(
2772 sc->sc_current_rx_bytes = (temp + 3) & ~3;
2775 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
2895 uint32_t temp;
2899 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
2905 if (temp != 0)
2906 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp);
2960 uint32_t temp;
2980 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
2981 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI)
3089 uint32_t temp;
3091 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
3093 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
3096 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
3110 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp)
3115 td = temp->td_next;
3116 temp->td = td;
3119 temp->td_next = td->obj_next;
3122 td->func = temp->func;
3123 td->pc = temp->pc;
3124 td->offset = temp->offset;
3125 td->remainder = temp->len;
3130 td->did_stall = temp->did_stall;
3131 td->short_pkt = temp->short_pkt;
3132 td->alt_next = temp->setup_alt_next;
3148 struct dwc_otg_std_temp temp;
3158 temp.max_frame_size = xfer->max_frame_size;
3164 /* setup temp */
3166 temp.pc = NULL;
3167 temp.td = NULL;
3168 temp.td_next = xfer->td_start[0];
3169 temp.offset = 0;
3170 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3172 temp.did_stall = !xfer->flags_int.control_stall;
3182 temp.func = &dwc_otg_host_setup_tx;
3184 temp.func = &dwc_otg_setup_rx;
3186 temp.len = xfer->frlengths[0];
3187 temp.pc = xfer->frbuffers + 0;
3188 temp.short_pkt = temp.len ? 1 : 0;
3194 temp.setup_alt_next = 0;
3197 dwc_otg_setup_standard_chain_sub(&temp);
3207 temp.func = &dwc_otg_host_data_rx;
3210 temp.func = &dwc_otg_data_tx;
3215 temp.func = &dwc_otg_host_data_tx;
3218 temp.func = &dwc_otg_data_rx;
3224 temp.pc = xfer->frbuffers + x;
3232 temp.len = xfer->frlengths[x];
3239 temp.setup_alt_next = 0;
3242 temp.setup_alt_next = 0;
3245 if (temp.len == 0) {
3249 temp.short_pkt = 0;
3255 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3258 dwc_otg_setup_standard_chain_sub(&temp);
3261 temp.offset += temp.len;
3264 temp.pc = xfer->frbuffers + x;
3271 temp.pc = xfer->frbuffers + 0;
3272 temp.len = 0;
3273 temp.short_pkt = 0;
3274 temp.setup_alt_next = 0;
3279 temp.func = &dwc_otg_data_tx_sync;
3280 dwc_otg_setup_standard_chain_sub(&temp);
3292 temp.func = &dwc_otg_host_data_tx;
3295 temp.func = &dwc_otg_data_rx;
3300 temp.func = &dwc_otg_host_data_rx;
3303 temp.func = &dwc_otg_data_tx;
3308 dwc_otg_setup_standard_chain_sub(&temp);
3311 td = temp.td;
3316 temp.func = &dwc_otg_data_tx_sync;
3317 dwc_otg_setup_standard_chain_sub(&temp);
3324 temp.pc = xfer->frbuffers + 0;
3325 temp.len = 0;
3326 temp.short_pkt = 0;
3327 temp.setup_alt_next = 0;
3330 temp.func = &dwc_otg_data_tx_sync;
3331 dwc_otg_setup_standard_chain_sub(&temp);
3336 td = temp.td;
3689 uint32_t temp;
3712 temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3715 temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3719 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3720 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
3745 uint32_t temp;
3763 temp = DIEPCTL_EPTYPE_SET(
3767 temp = DIEPCTL_EPTYPE_SET(
3771 temp = DIEPCTL_EPTYPE_SET(
3776 temp |= DIEPCTL_MPS_SET(mps);
3777 temp |= DIEPCTL_TXFNUM_SET(ep_no);
3780 sc->sc_in_ctl[ep_no] = temp;
3782 sc->sc_out_ctl[ep_no] = temp;
3784 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3785 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
3786 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
3876 uint32_t temp;
3892 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
3893 DPRINTF("Version = 0x%08x\n", temp);
3910 temp = GUSBCFG_FORCEDEVMODE;
3913 temp = GUSBCFG_FORCEHOSTMODE;
3916 temp = 0;
3925 GUSBCFG_TRD_TIM_SET(5) | temp);
3929 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3931 temp & ~GLPMCFG_HSIC_CONN);
3933 temp | GLPMCFG_HSIC_CONN);
3938 GUSBCFG_TRD_TIM_SET(5) | temp);
3941 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3943 temp & ~GLPMCFG_HSIC_CONN);
3948 GUSBCFG_TRD_TIM_SET(5) | temp);
3951 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3953 temp & ~GLPMCFG_HSIC_CONN);
3955 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO);
3956 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN);
3957 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN |
3959 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp);
3982 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
3984 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3986 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3988 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
3993 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
3998 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
4000 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
4019 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
4020 if (temp & GHWCFG2_MPI) {
4039 temp = DWC_OTG_READ_4(sc, DOTG_HCFG);
4040 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK);
4041 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT);
4042 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp);
4054 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
4056 DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
4059 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
4186 uint32_t temp;
4195 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM);
4198 framenum = (temp & HFNUM_FRNUM_MASK);
4200 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
4203 framenum = DSTS_SOFFN_GET(temp);
4227 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK;
4229 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) {
4244 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK;
4250 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes;