usb/controller/dwc_otg.c

362 		/* reset host channel state */
365 		/* enable all host channel interrupts */
369 		/* enable proper host channel interrupts */
434 	    /* enable proper device channel interrupts */
452 		/* reset host channel state */
764 	if (td->channel[0] < DWC_OTG_MAX_CHANNELS)
778 		/* check if channel is allocated */
781 		/* check if channel is still enabled */
784 		/* store channel number */
785 		td->channel[y++] = x;
791 		/* reset channel variable */
792 		td->channel[0] = DWC_OTG_MAX_CHANNELS;
793 		td->channel[1] = DWC_OTG_MAX_CHANNELS;
794 		td->channel[2] = DWC_OTG_MAX_CHANNELS;
801 		x = td->channel[y];
815 		/* set active channel */
827 	if (td->channel[index] >= DWC_OTG_MAX_CHANNELS)
830 	/* free channel */
831 	x = td->channel[index];
832 	td->channel[index] = DWC_OTG_MAX_CHANNELS;
838 	 * else the host channel will stop functioning.
848 	/* clear active channel */
855 	/* disable host channel */
858 		DPRINTF("Halting channel %d\n", x);
861 		/* don't write HCCHAR until the channel is halted */
883 		if (td->channel[x] >= DWC_OTG_MAX_CHANNELS ||
884 		    td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status))
901 	if (td->channel[0] < DWC_OTG_MAX_CHANNELS) {
902 		hcint = sc->sc_chan_state[td->channel[0]].hcint;
905 		    td->channel[0], td->state, hcint,
906 		    DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])),
907 		    DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0])));
917 		DPRINTF("CH=%d STALL\n", td->channel[0]);
922 		DPRINTF("CH=%d ERROR\n", td->channel[0]);
989 	/* free existing channel, if any */
1012 	/* allocate a new channel */
1028 	DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1033 	DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1039 	/* must enable channel before writing data to FIFO */
1040 	DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1044 	    DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4);
1054 	/* free existing channel, if any */
1069 	/* allocate a new channel */
1081 	DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1084 	DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1090 	/* must enable channel before writing data to FIFO */
1091 	DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1262     uint8_t channel)
1270 	if (channel >= DWC_OTG_MAX_CHANNELS)
1273 	if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel)
1282 		if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) {
1345 		sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY;
1364 	uint8_t channel;
1368 		channel = td->channel[x];
1369 		if (channel >= DWC_OTG_MAX_CHANNELS)
1371 		hcint |= sc->sc_chan_state[channel].hcint;
1374 		    channel, td->state, hcint,
1375 		    DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1376 		    DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1383 			DPRINTF("CH=%d STALL\n", channel);
1388 			DPRINTF("CH=%d ERROR\n", channel);
1399 		if (dwc_otg_host_data_rx_sub(sc, td, channel))
1403 		hcint |= sc->sc_chan_state[channel].hcint;
1530 	/* free existing channel, if any */
1556 	/* allocate a new channel */
1571 	  	channel = td->channel[x];
1574 		DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1580 		DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1603 		/* must enable channel before data can be received */
1604 		DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1612 	/* free existing channel(s), if any */
1628 	/* allocate a new channel */
1634 	channel = td->channel[0];
1640 	DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1643 	DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1658 	/* must enable channel before data can be received */
1659 	DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1803 	uint8_t channel;
1808 	/* check that last channel is complete */
1809 	channel = td->channel[td->npkt];
1811 	if (channel < DWC_OTG_MAX_CHANNELS) {
1812 		hcint = sc->sc_chan_state[channel].hcint;
1815 		    channel, td->state, hcint,
1816 		    DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1817 		    DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1823 			DPRINTF("CH=%d STALL\n", channel);
1828 			DPRINTF("CH=%d ERROR\n", channel);
1933 	/* free existing channel(s), if any */
1954 	/* allocate a new channel */
1996 		channel = td->channel[x];
2010 				DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2017 				DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2023 				DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2032 			DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2039 			DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2046 		DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2059 		DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2064 			    td->tx_bytes, DOTG_DFIFO(channel), count);
2080 	/* free existing channel, if any */
2096 	/* allocate a new channel */
2102 	channel = td->channel[0];
2107 	DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2110 	DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2122 	/* must enable channel before data can be received */
2123 	DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2718 	/* get all host channel interrupts */
2751 				/* check for halted channel */
2755 					DPRINTFN(5, "channel halt complete ch=%u\n", ep_no);
3136 	td->channel[0] = DWC_OTG_MAX_CHANNELS;
3137 	td->channel[1] = DWC_OTG_MAX_CHANNELS;
3138 	td->channel[2] = DWC_OTG_MAX_CHANNELS;