dev/sn/if_sn.c

161 	struct sn_softc *sc = device_get_softc(dev);
170 	ifp = sc->ifp = if_alloc(IFT_ETHER);
176 	SN_LOCK_INIT(sc);
177 	callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
178 	snstop(sc);
179 	sc->pages_wanted = -1;
182 		SMC_SELECT_BANK(sc, 3);
183 		rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
188 		SMC_SELECT_BANK(sc, 1);
189 		i = CSR_READ_2(sc, CONFIG_REG_W);
197 	SMC_SELECT_BANK(sc, 1);
200 		address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
204 	ifp->if_softc = sc;
222 	if ((err = bus_setup_intr(dev, sc->irq_res,
223 	    INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
224 	    &sc->intrhand)) != 0) {
238 	struct sn_softc	*sc = device_get_softc(dev);
239 	struct ifnet	*ifp = sc->ifp;
242 	SN_LOCK(sc);
243 	snstop(sc);
244 	SN_UNLOCK(sc);
245 	callout_drain(&sc->watchdog);
248 	SN_LOCK_DESTROY(sc);
255 	struct sn_softc *sc = xsc;
256 	SN_LOCK(sc);
257 	sninit_locked(sc);
258 	SN_UNLOCK(sc);
267 	struct sn_softc *sc = xsc;
268 	struct ifnet *ifp = sc->ifp;
272 	SN_ASSERT_LOCKED(sc);
279 	SMC_SELECT_BANK(sc, 0);
280 	CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
281 	SMC_DELAY(sc);
282 	CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
283 	SMC_DELAY(sc);
284 	SMC_DELAY(sc);
286 	CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
293 	SMC_SELECT_BANK(sc, 1);
294 	CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
298 	flags = CSR_READ_2(sc, CONFIG_REG_W);
300 	CSR_WRITE_2(sc, CONFIG_REG_W, flags);
305 	SMC_SELECT_BANK(sc, 2);
306 	CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
307 	while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY)	/* NOTHING */
313 	CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
315 	sn_setmcast(sc);
329 	CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
335 	SMC_SELECT_BANK(sc, 2);
342 	CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
343 	sc->intr_mask = mask;
344 	sc->pages_wanted = -1;
352 	callout_reset(&sc->watchdog, hz, snwatchdog, sc);
363 	struct sn_softc *sc = ifp->if_softc;
364 	SN_LOCK(sc);
366 	SN_UNLOCK(sc);
373 	struct sn_softc *sc = ifp->if_softc;
385 	SN_ASSERT_LOCKED(sc);
389 	if (sc->pages_wanted != -1) {
445 	SMC_SELECT_BANK(sc, 2);
446 	CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
456 		if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
470 		mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
471 		CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
472 		sc->intr_mask = mask;
474 		sc->timer = 1;
476 		sc->pages_wanted = numPages;
482 	packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
491 	CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
496 	CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
502 	CSR_WRITE_2(sc, DATA_REG_W, 0);
503 	CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
504 	CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
520 		CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
527 			CSR_WRITE_1(sc, DATA_REG_B,
535 		CSR_WRITE_2(sc, DATA_REG_W, 0);
539 		CSR_WRITE_1(sc, DATA_REG_B, 0);
546 	CSR_WRITE_2(sc, DATA_REG_W, 0);
552 	mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
553 	CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
554 	sc->intr_mask = mask;
556 	CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
559 	sc->timer = 1;
574 	if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
592 	struct sn_softc *sc = ifp->if_softc;
603 	if (sc->pages_wanted < 0)
606 	pages_wanted = sc->pages_wanted;
607 	sc->pages_wanted = -1;
659 	SMC_SELECT_BANK(sc, 2);
665 	packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
668 		sc->timer = 1;
674 	CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
686 		while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY)	/* NOTHING */
688 		CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
695 	CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
701 	CSR_WRITE_2(sc, DATA_REG_W, 0);
702 	CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
703 	CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
719 		CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
725 			CSR_WRITE_1(sc, DATA_REG_B,
733 		CSR_WRITE_2(sc, DATA_REG_W, 0);
737 		CSR_WRITE_1(sc, DATA_REG_B, 0);
744 	CSR_WRITE_2(sc, DATA_REG_W, 0);
750 	mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
751 	CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
752 	sc->intr_mask = mask;
753 	CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
773 	sc->timer = 1;
781 	struct sn_softc *sc = (struct sn_softc *) arg;
783 	SN_LOCK(sc);
784 	snintr_locked(sc);
785 	SN_UNLOCK(sc);
789 snintr_locked(struct sn_softc *sc)
792 	struct ifnet   *ifp = sc->ifp;
805 	sc->timer = 0;
807 	SMC_SELECT_BANK(sc, 2);
813 	mask = CSR_READ_1(sc, INTR_MASK_REG_B);
814 	CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
820 	interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
834 		SMC_SELECT_BANK(sc, 2);
835 		CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
845 		SMC_SELECT_BANK(sc, 2);
846 		packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
876 		SMC_SELECT_BANK(sc, 2);
877 		CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
879 		packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
885 		CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
890 		CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
897 		tx_status = CSR_READ_2(sc, DATA_REG_W);
900 			device_printf(sc->dev,
913 		SMC_SELECT_BANK(sc, 0);
916 		CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
918 		CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
924 		SMC_SELECT_BANK(sc, 2);
925 		while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY)	/* NOTHING */
927 		CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
944 		SMC_SELECT_BANK(sc, 2);
945 		CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
952 		SMC_SELECT_BANK(sc, 0);
953 		card_stats = CSR_READ_2(sc, COUNTER_REG_W);
965 		SMC_SELECT_BANK(sc, 2);
977 		snstop(sc);
978 		sninit_locked(sc);
986 	SMC_SELECT_BANK(sc, 2);
995 	mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
996 	CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
997 	sc->intr_mask = mask;
1003         struct sn_softc *sc = ifp->if_softc;
1011 	SMC_SELECT_BANK(sc, 2);
1013 	packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1030 	CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1035 	status = CSR_READ_2(sc, DATA_REG_W);
1036 	packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1086 	CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1089 		*data = CSR_READ_1(sc, DATA_REG_B);
1105 	SN_UNLOCK(sc);
1107 	SN_LOCK(sc);
1115 	SMC_SELECT_BANK(sc, 2);
1116 	while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY)	/* NOTHING */
1118 	CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1123 	packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1139 	struct sn_softc *sc = ifp->if_softc;
1144 		SN_LOCK(sc);
1147 			snstop(sc);
1150 			sninit_locked(sc);
1152 		SN_UNLOCK(sc);
1158 		SN_LOCK(sc);
1159 		sn_setmcast(sc);
1161 		SN_UNLOCK(sc);
1173 	struct sn_softc *sc;
1175 	sc = arg;
1176 	SN_ASSERT_LOCKED(sc);
1177 	callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1178 	if (sc->timer == 0 || --sc->timer > 0)
1180 	snintr_locked(sc);
1189 snstop(struct sn_softc *sc)
1192 	struct ifnet   *ifp = sc->ifp;
1197 	SMC_SELECT_BANK(sc, 2);
1198 	CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1203 	SMC_SELECT_BANK(sc, 0);
1204 	CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1205 	CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1210 	sc->timer = 0;
1211 	callout_stop(&sc->watchdog);
1219 	struct sn_softc *sc = device_get_softc(dev);
1221 	sc->port_rid = 0;
1222 	sc->port_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT,
1223 	    &sc->port_rid, SMC_IO_EXTENT, RF_ACTIVE);
1224 	if (!sc->port_res) {
1230 	sc->irq_rid = 0;
1231 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1233 	if (!sc->irq_res) {
1245 	struct sn_softc *sc = device_get_softc(dev);
1247 	if (sc->intrhand)
1248 		bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1249 	sc->intrhand = 0;
1250 	if (sc->port_res)
1251 		bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1252 		    sc->port_res);
1253 	sc->port_res = 0;
1254 	if (sc->modem_res)
1255 		bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1256 		    sc->modem_res);
1257 	sc->modem_res = 0;
1258 	if (sc->irq_res)
1259 		bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1260 		    sc->irq_res);
1261 	sc->irq_res = 0;
1283 	struct sn_softc *sc = device_get_softc(dev);
1295 	bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1307 	CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1308 	bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1322 	CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1323 	base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1325 	if (rman_get_start(sc->port_res) != base_address_register) {
1334 		    rman_get_start(sc->port_res), base_address_register);
1344 	CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1345 	revision_register = CSR_READ_2(sc, REVISION_REG_W);
1372 sn_setmcast(struct sn_softc *sc)
1374 	struct ifnet *ifp = sc->ifp;
1378 	SN_ASSERT_LOCKED(sc);
1394 			SMC_SELECT_BANK(sc, 3);
1395 			CSR_WRITE_2(sc, MULTICAST1_REG_W,
1397 			CSR_WRITE_2(sc, MULTICAST2_REG_W,
1399 			CSR_WRITE_2(sc, MULTICAST3_REG_W,
1401 			CSR_WRITE_2(sc, MULTICAST4_REG_W,
1407 	SMC_SELECT_BANK(sc, 0);
1408 	CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);