Lines Matching refs:val
177 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val)
180 bus_write_1(sc->smc_reg, offset, val);
191 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val)
194 bus_write_2(sc->smc_reg, offset, val);
225 uint16_t val;
246 val = bus_read_2(reg, BSR);
247 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
259 val = bus_read_2(reg, BSR);
260 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
271 val = bus_read_2(reg, BAR);
272 val = BAR_ADDRESS(val);
273 if (rman_get_start(reg) != val) {
276 "I/O resource address %lx\n", val,
285 val = bus_read_2(reg, REV);
286 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
287 if (smc_chip_ids[val] == NULL) {
289 device_printf(dev, "Unknown chip revision: %d\n", val);
294 device_set_desc(dev, smc_chip_ids[val]);
305 uint16_t val;
350 val = smc_read_2(sc, REV);
351 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
352 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
954 uint32_t val;
964 val = smc_read_2(sc, MGMT);
968 return (val);
972 smc_mii_bitbang_write(device_t dev, uint32_t val)
984 smc_write_2(sc, MGMT, val);
993 int val;
1001 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);
1004 return (val);