dev/smartpqi/smartpqi_sis.c

32 void sis_disable_msix(pqisrc_softstate_t *softs)
38 	db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
41 	PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
48 void pqisrc_trigger_nmi_sis(pqisrc_softstate_t *softs)
53 	PCI_MEM_PUT32(softs,  &softs->ioa_reg->host_to_ioa_db,
59 int pqisrc_reenable_sis(pqisrc_softstate_t *softs)
66 	PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
69 	COND_WAIT(((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &
81 int pqisrc_check_fw_status(pqisrc_softstate_t *softs)
89 	COND_WAIT((GET_FW_STATUS(softs) &
101 static int pqisrc_send_sis_cmd(pqisrc_softstate_t *softs,
115 		PCI_MEM_PUT32(softs, &softs->ioa_reg->mb[i],
118 	PCI_MEM_PUT32(softs, &softs->ioa_reg->ioa_to_host_db_clr,
122 	PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
130 	val = PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R);
134 	COND_WAIT((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &
142 	mb[0] = LE_32(PCI_MEM_GET32(softs, &softs->ioa_reg->mb[0], LEGACY_SIS_SRCV_MAILBOX));
153 		mb[i] =	LE_32(PCI_MEM_GET32(softs, &softs->ioa_reg->mb[i], LEGACY_SIS_SRCV_MAILBOX+i*4));
164 int pqisrc_get_adapter_properties(pqisrc_softstate_t *softs,
173 	ret = pqisrc_send_sis_cmd(softs, mb);
186 int pqisrc_get_preferred_settings(pqisrc_softstate_t *softs)
194 	ret = pqisrc_send_sis_cmd(softs, mb);
197 		softs->pref_settings.max_cmd_size = mb[1] >> 16;
199 		softs->pref_settings.max_fib_size = mb[1] & 0x0000FFFF;
201 			softs->pref_settings.max_cmd_size,
202 			softs->pref_settings.max_fib_size);
210 int pqisrc_get_sis_pqi_cap(pqisrc_softstate_t *softs)
218 	ret = pqisrc_send_sis_cmd(softs,  mb);
220 		softs->pqi_cap.max_sg_elem = mb[1];
221 		softs->pqi_cap.max_transfer_size = mb[2];
222 		softs->pqi_cap.max_outstanding_io = mb[3];
224 		softs->os_specific.buf_dma_attr.dma_attr_sgllen =
225 				softs->pqi_cap.max_sg_elem;
226 		softs->os_specific.buf_dma_attr.dma_attr_maxxfer =
227 				softs->pqi_cap.max_transfer_size;
228 		softs->os_specific.buf_dma_attr.dma_attr_count_max =
229 				softs->pqi_cap.max_transfer_size - 1;
231 		softs->pqi_cap.conf_tab_off = mb[4];
233 		softs->pqi_cap.conf_tab_sz =  mb[5];
236 					softs->pqi_cap.max_sg_elem);
238 					softs->pqi_cap.max_transfer_size);
240 					softs->pqi_cap.max_outstanding_io);
248 int pqisrc_init_struct_base(pqisrc_softstate_t *softs)
264 	ret = os_dma_mem_alloc(softs, &init_struct_mem);
272 	/* The valid tag values are from 1, 2, ..., softs->max_outstanding_io
276 	num_elem = softs->pqi_cap.max_outstanding_io + 1;
278 	softs->err_buf_dma_mem.size = num_elem * elem_size;
281 	softs->err_buf_dma_mem.align = PQISRC_ERR_BUF_DMA_ALIGN;
282 	softs->err_buf_dma_mem.tag = "error_buffer";
283 	ret = os_dma_mem_alloc(softs, &softs->err_buf_dma_mem);
294 	init_struct->err_buf_paddr_l = DMA_PHYS_LOW(&softs->err_buf_dma_mem);
295 	init_struct->err_buf_paddr_h = DMA_PHYS_HIGH(&softs->err_buf_dma_mem);
304 	ret = pqisrc_send_sis_cmd(softs, mb);
309 	os_dma_mem_free(softs, &init_struct_mem);
313 	os_dma_mem_free(softs, &softs->err_buf_dma_mem);
315 	os_dma_mem_free(softs, &init_struct_mem);
328 int pqisrc_sis_init(pqisrc_softstate_t *softs)
336 	ret = pqisrc_force_sis(softs);
343 	ret = pqisrc_check_fw_status(softs);
350 	ret = pqisrc_get_adapter_properties(softs, &prop, &ext_prop);
362 	softs->pqi_reset_quiesce_allowed = false;
364 		softs->pqi_reset_quiesce_allowed = true;
367 	ret = pqisrc_get_preferred_settings(softs);
374 	ret = pqisrc_get_sis_pqi_cap(softs);
383 	ret = os_dma_setup(softs);
390 	ret = pqisrc_init_struct_base(softs);
401 	os_dma_destroy(softs);
408 void pqisrc_sis_uninit(pqisrc_softstate_t *softs)
412 	os_dma_mem_free(softs, &softs->err_buf_dma_mem);
414 	os_dma_destroy(softs);
415 	os_resource_free(softs);
416 	pqi_reset(softs);
422 int pqisrc_sis_wait_for_db_bit_to_clear(pqisrc_softstate_t *softs, uint32_t bit)
431 		db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
435 		if (GET_FW_STATUS(softs) & PQI_CTRL_KERNEL_PANIC) {