sfxge/common/siena_phy.c

466 	__inout_ecount_opt(EFX_PHY_NSTATS)	uint32_t *stat)
472 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);
473 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);
474 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);
475 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);
482 		if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
488 			stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;
489 			stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;
490 			stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;
491 			stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;
495 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,
497 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,
499 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,
501 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,
504 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);
505 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);
506 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);
507 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);
508 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);
510 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,
512 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,
514 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,
516 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,
524 		if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
529 			stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;
530 			stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;
531 			stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;
532 			stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;
536 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);
537 	SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);
539 	SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,
550 	__inout_ecount(EFX_PHY_NSTATS)		uint32_t *stat)
579 	siena_phy_decode_stats(enp, vmask, esmp, &smask, stat);