Lines Matching refs:slot
72 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
73 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
74 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
75 #define RD_MULTI_4(slot, off, ptr, count) \
76 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
78 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
79 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
80 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
81 #define WR_MULTI_4(slot, off, ptr, count) \
82 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
84 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
87 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
88 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
89 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
90 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
92 static void sdhci_finish_command(struct sdhci_slot *slot);
93 static void sdhci_init(struct sdhci_slot *slot);
94 static void sdhci_read_block_pio(struct sdhci_slot *slot);
95 static void sdhci_req_done(struct sdhci_slot *slot);
97 static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask);
99 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
100 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
101 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
103 static void sdhci_start(struct sdhci_slot *slot);
105 static void sdhci_start_command(struct sdhci_slot *slot,
107 static void sdhci_start_data(struct sdhci_slot *slot,
109 static void sdhci_write_block_pio(struct sdhci_slot *slot);
110 static void sdhci_transfer_pio(struct sdhci_slot *slot);
113 static int sdhci_dma_alloc(struct sdhci_slot *slot);
114 static void sdhci_dma_free(struct sdhci_slot *slot);
115 static void sdhci_dumpregs(struct sdhci_slot *slot);
118 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
120 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot);
125 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
164 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
169 retval = printf("%s-slot%d: ",
170 device_get_nameunit(slot->bus), slot->num);
179 sdhci_dumpregs(struct sdhci_slot *slot)
182 slot_printf(slot,
185 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
186 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
187 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
188 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
189 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
190 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
191 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
192 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
193 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
194 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
195 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
196 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
197 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
198 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
199 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
200 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
201 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n",
202 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2));
203 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n",
204 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));
205 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n",
206 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));
207 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n",
208 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS));
210 slot_printf(slot,
215 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
220 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
221 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
227 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
229 clock = slot->clock;
230 slot->clock = 0;
231 sdhci_set_clock(slot, clock);
235 slot->clock = 0;
236 slot->power = 0;
239 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
241 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
251 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
262 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
264 slot_printf(slot, "Reset 0x%x never completed.\n",
266 sdhci_dumpregs(slot);
275 sdhci_tuning_intmask(const struct sdhci_slot *slot)
280 if (slot->opt & SDHCI_TUNING_ENABLED) {
282 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 ||
283 slot->retune_mode == SDHCI_RETUNE_MODE_3)
290 sdhci_init(struct sdhci_slot *slot)
293 sdhci_reset(slot, SDHCI_RESET_ALL);
296 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
303 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
304 !(slot->opt & SDHCI_NON_REMOVABLE)) {
305 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
308 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
309 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
313 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
322 if (clock == slot->clock)
324 slot->clock = clock;
327 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
328 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
334 clk_base = slot->max_clk;
335 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) {
336 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) &
351 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);
355 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
356 slot->timeout_clk = slot->clock / 1000;
358 if (slot->version < SDHCI_SPEC_300) {
382 slot_printf(slot, "Divider %d for freq %d (base %d)\n",
390 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
393 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
396 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
399 slot_printf(slot,
401 sdhci_dumpregs(slot);
409 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
413 sdhci_set_power(struct sdhci_slot *slot, u_char power)
418 if (slot->power == power)
421 slot->power = power;
425 WR1(slot, SDHCI_POWER_CONTROL, pwr);
443 WR1(slot, SDHCI_POWER_CONTROL, pwr);
451 WR1(slot, SDHCI_POWER_CONTROL, pwr);
452 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)
456 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON))
457 slot_printf(slot, "Bus power failed to enable");
459 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) {
460 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
462 WR1(slot, SDHCI_POWER_CONTROL, pwr);
468 sdhci_read_block_pio(struct sdhci_slot *slot)
474 buffer = slot->curcmd->data->data;
475 buffer += slot->offset;
477 left = min(512, slot->curcmd->data->len - slot->offset);
478 slot->offset += left;
481 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
486 data = RD4(slot, SDHCI_BUFFER);
495 RD_MULTI_4(slot, SDHCI_BUFFER,
501 data = RD4(slot, SDHCI_BUFFER);
511 sdhci_write_block_pio(struct sdhci_slot *slot)
517 buffer = slot->curcmd->data->data;
518 buffer += slot->offset;
520 left = min(512, slot->curcmd->data->len - slot->offset);
521 slot->offset += left;
532 WR4(slot, SDHCI_BUFFER, data);
535 WR_MULTI_4(slot, SDHCI_BUFFER,
546 WR4(slot, SDHCI_BUFFER, data);
551 sdhci_transfer_pio(struct sdhci_slot *slot)
555 if (slot->curcmd->data->flags & MMC_DATA_READ) {
556 while (RD4(slot, SDHCI_PRESENT_STATE) &
558 sdhci_read_block_pio(slot);
559 if (slot->offset >= slot->curcmd->data->len)
563 while (RD4(slot, SDHCI_PRESENT_STATE) &
565 sdhci_write_block_pio(slot);
566 if (slot->offset >= slot->curcmd->data->len)
575 struct sdhci_slot *slot = arg;
578 SDHCI_LOCK(slot);
579 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
580 if (slot->dev == NULL) {
583 slot_printf(slot, "Card inserted\n");
584 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
585 SDHCI_UNLOCK(slot);
587 device_set_ivars(d, slot);
591 SDHCI_UNLOCK(slot);
593 if (slot->dev != NULL) {
596 slot_printf(slot, "Card removed\n");
597 d = slot->dev;
598 slot->dev = NULL;
599 slot->intmask &= ~sdhci_tuning_intmask(slot);
600 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
601 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
602 slot->opt &= ~SDHCI_TUNING_ENABLED;
603 SDHCI_UNLOCK(slot);
604 callout_drain(&slot->retune_callout);
605 device_delete_child(slot->bus, d);
607 SDHCI_UNLOCK(slot);
612 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present)
627 was_present = slot->dev != NULL;
630 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
632 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
637 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present)
640 SDHCI_LOCK(slot);
641 sdhci_handle_card_present_locked(slot, is_present);
642 SDHCI_UNLOCK(slot);
648 struct sdhci_slot *slot = arg;
650 sdhci_handle_card_present(slot,
651 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
652 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
653 sdhci_card_poll, slot);
657 sdhci_dma_alloc(struct sdhci_slot *slot)
661 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) {
663 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
665 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K;
667 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K;
669 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K;
671 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K;
673 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K;
675 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K;
677 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K;
679 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary);
688 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz,
690 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW,
691 NULL, NULL, &slot->dmatag);
693 slot_printf(slot, "Can't create DMA tag for SDMA\n");
697 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
698 BUS_DMA_NOWAIT, &slot->dmamap);
700 slot_printf(slot, "Can't alloc DMA memory for SDMA\n");
701 bus_dma_tag_destroy(slot->dmatag);
705 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
706 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr,
707 &slot->paddr, 0);
708 if (err != 0 || slot->paddr == 0) {
709 slot_printf(slot, "Can't load DMA memory for SDMA\n");
710 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
711 bus_dma_tag_destroy(slot->dmatag);
722 sdhci_dma_free(struct sdhci_slot *slot)
725 bus_dmamap_unload(slot->dmatag, slot->dmamap);
726 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
727 bus_dma_tag_destroy(slot->dmatag);
731 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
738 SDHCI_LOCK_INIT(slot);
740 slot->num = num;
741 slot->bus = dev;
743 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
745 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
746 caps = slot->caps;
747 caps2 = slot->caps2;
749 caps = RD4(slot, SDHCI_CAPABILITIES);
750 if (slot->version >= SDHCI_SPEC_300)
751 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
755 if (slot->version >= SDHCI_SPEC_300) {
758 slot_printf(slot,
760 SDHCI_LOCK_DESTROY(slot);
764 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
768 if (slot->version >= SDHCI_SPEC_300)
775 slot->max_clk = freq * 1000000;
781 if (slot->max_clk == 0) {
782 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
783 slot_printf(slot, "Hardware doesn't specify base clock "
788 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
789 slot->timeout_clk = slot->max_clk / 1000;
790 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
791 slot->timeout_clk = 1000;
793 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
796 slot->timeout_clk *= 1000;
803 if (slot->timeout_clk == 0) {
804 slot_printf(slot, "Hardware doesn't specify timeout clock "
806 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
809 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
810 slot->host.f_max = slot->max_clk;
811 slot->host.host_ocr = 0;
813 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
815 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
817 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
818 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
819 if (slot->host.host_ocr == 0) {
820 slot_printf(slot, "Hardware doesn't report any "
829 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
831 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
839 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
844 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
846 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
848 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
851 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 &&
891 slot->opt |= SDHCI_TUNING_SUPPORTED;
892 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
894 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
896 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
899 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
900 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
902 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
903 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
905 if (slot->retune_count > 0xb) {
906 slot_printf(slot, "Unknown re-tuning count "
907 "%x, using 1 sec\n", slot->retune_count);
908 slot->retune_count = 1;
909 } else if (slot->retune_count != 0)
910 slot->retune_count =
911 1 << (slot->retune_count - 1);
945 slot->host.caps = host_caps;
949 slot->opt |= SDHCI_HAVE_DMA;
951 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
952 slot->opt &= ~SDHCI_HAVE_DMA;
953 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
954 slot->opt |= SDHCI_HAVE_DMA;
955 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
956 slot->opt |= SDHCI_NON_REMOVABLE;
962 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
963 slot->opt &= ~SDHCI_HAVE_DMA;
965 if (slot->opt & SDHCI_HAVE_DMA) {
966 err = sdhci_dma_alloc(slot);
968 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
969 free(slot->tune_req, M_DEVBUF);
970 free(slot->tune_cmd, M_DEVBUF);
971 free(slot->tune_data, M_DEVBUF);
973 SDHCI_LOCK_DESTROY(slot);
979 slot_printf(slot,
981 slot->max_clk / 1000000,
988 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
994 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
995 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
996 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
1000 slot_printf(slot, "eMMC:%s%s%s%s\n",
1010 slot_printf(slot, "UHS-I:%s%s%s%s%s\n",
1016 if (slot->opt & SDHCI_TUNING_SUPPORTED)
1017 slot_printf(slot, "Re-tuning count %d secs, mode %d\n",
1018 slot->retune_count, slot->retune_mode + 1);
1019 sdhci_dumpregs(slot);
1022 slot->timeout = 10;
1023 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1024 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1025 "timeout", CTLFLAG_RW, &slot->timeout, 0,
1027 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1028 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
1029 sdhci_card_task, slot);
1030 callout_init(&slot->card_poll_callout, 1);
1031 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1032 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1034 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1035 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1036 callout_reset(&slot->card_poll_callout,
1037 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1040 sdhci_init(slot);
1046 sdhci_start_slot(struct sdhci_slot *slot)
1049 sdhci_card_task(slot, 0);
1053 sdhci_cleanup_slot(struct sdhci_slot *slot)
1057 callout_drain(&slot->timeout_callout);
1058 callout_drain(&slot->card_poll_callout);
1059 callout_drain(&slot->retune_callout);
1060 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1061 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1063 SDHCI_LOCK(slot);
1064 d = slot->dev;
1065 slot->dev = NULL;
1066 SDHCI_UNLOCK(slot);
1068 device_delete_child(slot->bus, d);
1070 SDHCI_LOCK(slot);
1071 sdhci_reset(slot, SDHCI_RESET_ALL);
1072 SDHCI_UNLOCK(slot);
1073 if (slot->opt & SDHCI_HAVE_DMA)
1074 sdhci_dma_free(slot);
1075 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1076 free(slot->tune_req, M_DEVBUF);
1077 free(slot->tune_cmd, M_DEVBUF);
1078 free(slot->tune_data, M_DEVBUF);
1081 SDHCI_LOCK_DESTROY(slot);
1087 sdhci_generic_suspend(struct sdhci_slot *slot)
1095 callout_drain(&slot->retune_callout);
1096 SDHCI_LOCK(slot);
1097 slot->opt &= ~SDHCI_TUNING_ENABLED;
1098 sdhci_reset(slot, SDHCI_RESET_ALL);
1099 SDHCI_UNLOCK(slot);
1105 sdhci_generic_resume(struct sdhci_slot *slot)
1108 SDHCI_LOCK(slot);
1109 sdhci_init(slot);
1110 SDHCI_UNLOCK(slot);
1116 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot)
1119 if (slot->version >= SDHCI_SPEC_300)
1120 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1122 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1126 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot)
1129 if (slot->opt & SDHCI_NON_REMOVABLE)
1132 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1136 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot)
1141 if (slot->version < SDHCI_SPEC_300)
1144 SDHCI_ASSERT_LOCKED(slot);
1145 ios = &slot->host.ios;
1146 sdhci_set_clock(slot, 0);
1147 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1166 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1167 sdhci_set_clock(slot, ios->clock);
1173 struct sdhci_slot *slot = device_get_ivars(reqdev);
1174 struct mmc_ios *ios = &slot->host.ios;
1176 SDHCI_LOCK(slot);
1179 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1180 sdhci_init(slot);
1183 sdhci_set_clock(slot, ios->clock);
1184 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1186 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1187 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1189 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1190 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1192 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1193 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1198 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1199 slot->hostctrl |= SDHCI_CTRL_HISPD;
1201 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1202 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1203 SDHCI_SET_UHS_TIMING(brdev, slot);
1205 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1206 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1208 SDHCI_UNLOCK(slot);
1215 struct sdhci_slot *slot = device_get_ivars(reqdev);
1220 if (slot->version < SDHCI_SPEC_300)
1224 vccq = slot->host.ios.vccq;
1225 SDHCI_LOCK(slot);
1226 sdhci_set_clock(slot, 0);
1227 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1233 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1235 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1241 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1248 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1250 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1256 slot_printf(slot,
1262 sdhci_set_clock(slot, slot->host.ios.clock);
1263 SDHCI_UNLOCK(slot);
1270 struct sdhci_slot *slot = device_get_ivars(reqdev);
1271 const struct mmc_ios *ios = &slot->host.ios;
1277 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1280 slot->retune_ticks = slot->retune_count * hz;
1282 SDHCI_LOCK(slot);
1285 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1286 SDHCI_UNLOCK(slot);
1295 slot->retune_ticks = 0;
1302 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1306 SDHCI_UNLOCK(slot);
1310 tune_cmd = slot->tune_cmd;
1314 tune_data = tune_cmd->data = slot->tune_data;
1320 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1322 slot->opt &= ~SDHCI_TUNING_ENABLED;
1323 err = sdhci_exec_tuning(slot, true);
1325 slot->opt |= SDHCI_TUNING_ENABLED;
1326 slot->intmask |= sdhci_tuning_intmask(slot);
1327 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1328 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1329 if (slot->retune_ticks) {
1330 callout_reset(&slot->retune_callout, slot->retune_ticks,
1331 sdhci_retune, slot);
1334 SDHCI_UNLOCK(slot);
1341 struct sdhci_slot *slot = device_get_ivars(reqdev);
1344 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1348 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1351 SDHCI_LOCK(slot);
1352 err = sdhci_exec_tuning(slot, reset);
1360 * is enabled. Note that due to slot->retune_req not being cleared in
1364 if (slot->retune_ticks) {
1365 callout_reset(&slot->retune_callout, slot->retune_ticks,
1366 sdhci_retune, slot);
1368 SDHCI_UNLOCK(slot);
1373 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset)
1382 SDHCI_ASSERT_LOCKED(slot);
1383 if (slot->req != NULL)
1387 opt = slot->opt;
1388 slot->opt = opt & ~SDHCI_HAVE_DMA;
1394 intmask = slot->intmask;
1395 slot->intmask = SDHCI_INT_DATA_AVAIL;
1396 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1397 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1399 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1404 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1406 tune_req = slot->tune_req;
1407 tune_cmd = slot->tune_cmd;
1412 tune_req->done_data = slot;
1413 slot->req = tune_req;
1414 slot->flags = 0;
1415 sdhci_start(slot);
1417 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1420 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1430 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask
1434 slot->opt = opt;
1435 slot->intmask = intmask;
1436 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1438 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1442 slot->retune_req = 0;
1446 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1447 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1449 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1456 struct sdhci_slot *slot = arg;
1458 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1462 sdhci_req_done(struct sdhci_slot *slot)
1466 if (slot->req != NULL && slot->curcmd != NULL) {
1467 callout_stop(&slot->timeout_callout);
1468 req = slot->req;
1469 slot->req = NULL;
1470 slot->curcmd = NULL;
1478 struct sdhci_slot *slot;
1480 slot = req->done_data;
1488 struct sdhci_slot *slot = arg;
1490 if (slot->curcmd != NULL) {
1491 slot_printf(slot, "Controller timeout\n");
1492 sdhci_dumpregs(slot);
1493 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1494 slot->curcmd->error = MMC_ERR_TIMEOUT;
1495 sdhci_req_done(slot);
1497 slot_printf(slot, "Spurious timeout - no active command\n");
1502 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data)
1512 if (__predict_true(slot->req->stop != NULL &&
1513 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)))
1518 if (slot->flags & SDHCI_USE_DMA)
1521 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1525 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
1530 slot->curcmd = cmd;
1531 slot->cmd_done = 0;
1537 slot_printf(slot, "Unsupported response type!\n");
1539 sdhci_req_done(slot);
1547 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1548 slot->power == 0 ||
1549 slot->clock == 0) {
1551 sdhci_req_done(slot);
1564 if (cmd == slot->req->stop ||
1579 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1581 slot_printf(slot, "Controller never released "
1583 sdhci_dumpregs(slot);
1585 sdhci_req_done(slot);
1610 sdhci_start_data(slot, cmd->data);
1616 if (slot->data_done == 0) {
1617 WR4(slot, SDHCI_SIGNAL_ENABLE,
1618 slot->intmask &= ~SDHCI_INT_RESPONSE);
1621 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1623 sdhci_set_transfer_mode(slot, cmd->data);
1625 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1627 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1628 sdhci_timeout, slot);
1632 sdhci_finish_command(struct sdhci_slot *slot)
1638 slot->cmd_done = 1;
1644 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1645 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1646 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1649 if (slot->curcmd->error) {
1650 if (slot->curcmd->error == MMC_ERR_BADCRC)
1651 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1652 sdhci_reset(slot, SDHCI_RESET_CMD);
1653 sdhci_reset(slot, SDHCI_RESET_DATA);
1654 sdhci_start(slot);
1658 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1659 if (slot->curcmd->flags & MMC_RSP_136) {
1663 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1664 if (slot->quirks &
1666 slot->curcmd->resp[3 - i] = val;
1668 slot->curcmd->resp[3 - i] =
1674 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1677 if (slot->data_done)
1678 sdhci_start(slot);
1682 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data)
1687 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1688 slot->data_done = 1;
1692 slot->data_done = 0;
1696 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1701 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1708 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1712 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1718 if ((slot->opt & SDHCI_HAVE_DMA))
1719 slot->flags |= SDHCI_USE_DMA;
1721 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1723 slot->flags &= ~SDHCI_USE_DMA;
1725 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1727 slot->flags &= ~SDHCI_USE_DMA;
1729 if (slot->flags & SDHCI_USE_DMA) {
1730 sdma_bbufsz = slot->sdma_bbufsz;
1732 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1735 memcpy(slot->dmamem, data->data, ulmin(data->len,
1737 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1740 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1746 slot->intmask &= ~SDHCI_INT_DMA_END;
1748 slot->intmask |= SDHCI_INT_DMA_END;
1749 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1752 slot->offset = 0;
1754 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512));
1755 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
1758 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt);
1762 sdhci_finish_data(struct sdhci_slot *slot)
1764 struct mmc_data *data = slot->curcmd->data;
1770 if (!slot->cmd_done) {
1771 WR4(slot, SDHCI_SIGNAL_ENABLE,
1772 slot->intmask |= SDHCI_INT_RESPONSE);
1775 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
1776 slot->curcmd->data != NULL) {
1778 left = data->len - slot->offset;
1779 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1781 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1782 ulmin(left, slot->sdma_bbufsz));
1784 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1787 slot->data_done = 1;
1789 if (slot->curcmd->error) {
1790 if (slot->curcmd->error == MMC_ERR_BADCRC)
1791 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1792 sdhci_reset(slot, SDHCI_RESET_CMD);
1793 sdhci_reset(slot, SDHCI_RESET_DATA);
1794 sdhci_start(slot);
1798 if (slot->cmd_done)
1799 sdhci_start(slot);
1803 sdhci_start(struct sdhci_slot *slot)
1807 req = slot->req;
1811 if (!(slot->flags & CMD_STARTED)) {
1812 slot->flags |= CMD_STARTED;
1813 sdhci_start_command(slot, req->cmd);
1816 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
1817 !(slot->flags & STOP_STARTED) && req->stop) {
1818 slot->flags |= STOP_STARTED;
1819 sdhci_start_command(slot, req->stop);
1823 slot_printf(slot, "result: %d\n", req->cmd->error);
1825 ((slot->curcmd == req->stop &&
1826 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
1827 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1828 sdhci_reset(slot, SDHCI_RESET_CMD);
1829 sdhci_reset(slot, SDHCI_RESET_DATA);
1832 sdhci_req_done(slot);
1839 struct sdhci_slot *slot = device_get_ivars(reqdev);
1841 SDHCI_LOCK(slot);
1842 if (slot->req != NULL) {
1843 SDHCI_UNLOCK(slot);
1847 slot_printf(slot,
1853 slot->req = req;
1854 slot->flags = 0;
1855 sdhci_start(slot);
1856 SDHCI_UNLOCK(slot);
1858 while (slot->req != NULL) {
1859 sdhci_generic_intr(slot);
1869 struct sdhci_slot *slot = device_get_ivars(reqdev);
1872 SDHCI_LOCK(slot);
1873 val = RD4(slot, SDHCI_PRESENT_STATE);
1874 SDHCI_UNLOCK(slot);
1881 struct sdhci_slot *slot = device_get_ivars(reqdev);
1884 SDHCI_LOCK(slot);
1885 while (slot->bus_busy)
1886 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1887 slot->bus_busy++;
1889 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1890 SDHCI_UNLOCK(slot);
1897 struct sdhci_slot *slot = device_get_ivars(reqdev);
1899 SDHCI_LOCK(slot);
1901 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1902 slot->bus_busy--;
1903 SDHCI_UNLOCK(slot);
1904 wakeup(slot);
1909 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1912 if (!slot->curcmd) {
1913 slot_printf(slot, "Got command interrupt 0x%08x, but "
1915 sdhci_dumpregs(slot);
1919 slot->curcmd->error = MMC_ERR_TIMEOUT;
1921 slot->curcmd->error = MMC_ERR_BADCRC;
1923 slot->curcmd->error = MMC_ERR_FIFO;
1925 sdhci_finish_command(slot);
1929 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1935 if (!slot->curcmd) {
1936 slot_printf(slot, "Got data interrupt 0x%08x, but "
1938 sdhci_dumpregs(slot);
1941 if (slot->curcmd->data == NULL &&
1942 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1943 slot_printf(slot, "Got data interrupt 0x%08x, but "
1946 sdhci_dumpregs(slot);
1950 slot->curcmd->error = MMC_ERR_TIMEOUT;
1952 slot->curcmd->error = MMC_ERR_BADCRC;
1953 if (slot->curcmd->data == NULL &&
1956 slot_printf(slot, "Got data interrupt 0x%08x, but "
1958 sdhci_dumpregs(slot);
1959 slot->curcmd->error = MMC_ERR_INVALID;
1961 if (slot->curcmd->error) {
1968 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
1969 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
1970 slot->req->flags |= MMC_TUNE_DONE;
1971 sdhci_finish_command(slot);
1972 sdhci_finish_data(slot);
1977 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1978 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1979 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
1981 slot->flags |= PLATFORM_DATA_STARTED;
1983 sdhci_transfer_pio(slot);
1987 data = slot->curcmd->data;
1988 sdma_bbufsz = slot->sdma_bbufsz;
1991 left = data->len - slot->offset;
1993 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1995 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1998 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2002 slot->offset += sdma_bbufsz;
2003 left = data->len - slot->offset;
2005 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2008 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2010 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2018 slot->intmask &= ~SDHCI_INT_DMA_END;
2019 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2022 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2026 if (slot->flags & PLATFORM_DATA_STARTED) {
2027 slot->flags &= ~PLATFORM_DATA_STARTED;
2028 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2030 sdhci_finish_data(slot);
2033 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2034 if (slot->flags & PLATFORM_DATA_STARTED) {
2035 slot->flags &= ~PLATFORM_DATA_STARTED;
2036 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2038 sdhci_finish_data(slot);
2043 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err)
2046 if (!slot->curcmd) {
2047 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2049 sdhci_dumpregs(slot);
2052 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
2053 sdhci_reset(slot, SDHCI_RESET_CMD);
2057 sdhci_generic_intr(struct sdhci_slot *slot)
2062 SDHCI_LOCK(slot);
2063 /* Read slot interrupt status. */
2064 intmask = RD4(slot, SDHCI_INT_STATUS);
2066 SDHCI_UNLOCK(slot);
2070 slot_printf(slot, "Interrupt %#x\n", intmask);
2074 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2075 slot_printf(slot, "Tuning error indicated\n");
2076 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2077 if (slot->curcmd) {
2078 slot->curcmd->error = MMC_ERR_BADCRC;
2079 sdhci_finish_command(slot);
2084 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2088 slot->intmask &=
2090 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2092 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2093 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2094 WR4(slot, SDHCI_INT_STATUS, intmask &
2096 sdhci_handle_card_present_locked(slot, present);
2100 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2101 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2105 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2108 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2113 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2114 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2115 sdhci_acmd_irq(slot, val16);
2119 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2120 slot_printf(slot, "Card is consuming too much power!\n");
2127 WR4(slot, SDHCI_INT_STATUS, intmask);
2128 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2130 sdhci_dumpregs(slot);
2133 SDHCI_UNLOCK(slot);
2140 const struct sdhci_slot *slot = device_get_ivars(child);
2146 *result = slot->host.ios.bus_mode;
2149 *result = slot->host.ios.bus_width;
2152 *result = slot->host.ios.chip_select;
2155 *result = slot->host.ios.clock;
2158 *result = slot->host.f_min;
2161 *result = slot->host.f_max;
2164 *result = slot->host.host_ocr;
2167 *result = slot->host.mode;
2170 *result = slot->host.ocr;
2173 *result = slot->host.ios.power_mode;
2176 *result = slot->host.ios.vdd;
2179 if (slot->opt & SDHCI_TUNING_ENABLED) {
2180 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2184 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2192 *result = slot->host.ios.vccq;
2195 *result = slot->host.caps;
2198 *result = slot->host.ios.timing;
2205 if (slot->opt & SDHCI_TUNING_ENABLED &&
2206 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2207 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2227 struct sdhci_slot *slot = device_get_ivars(child);
2235 slot->host.ios.bus_mode = value;
2238 slot->host.ios.bus_width = value;
2241 slot->host.ios.chip_select = value;
2245 max_clock = slot->max_clk;
2248 if (slot->version < SDHCI_SPEC_300) {
2264 slot->host.ios.clock = clock;
2266 slot->host.ios.clock = 0;
2269 slot->host.mode = value;
2272 slot->host.ocr = value;
2275 slot->host.ios.power_mode = value;
2278 slot->host.ios.vdd = value;
2281 slot->host.ios.vccq = value;
2284 slot->host.ios.timing = value;