dev/sdhci/fsl_sdhci.c

182 static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val);
193 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val)
196 	bus_write_4(sc->mem_res, off, val);
375 fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
389 		val32 |= (val & SDHCI_CTRL_LED);
390 		if (val & SDHCI_CTRL_8BITBUS)
393 			val32 |= (val & SDHCI_CTRL_4BITBUS);
394 		val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4;
395 		val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD));
412 	val32 |= (val << (off & 3) * 8);
418 fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
428 		fsl_sdhc_set_clock(sc, val);
447 		if (val & SDHCI_CMD_DATA) {
453 			if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) {
472 			val32 |= val & 0x37;
480 			    (sc->cmd_and_mode & 0xffff0000) | val;
484 			    (sc->cmd_and_mode & 0xffff) | (val << 16);
492 	val32 |= ((val & 0xffff) << (off & 3) * 8);
497 fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
503 		sc->r1bfix_intmask &= ~val;
506 	WR4(sc, off, val);
521 	uint16_t val;
531 	val = sc->sdclockreg_freq_bits;
538 	val |= SDHCI_CLOCK_INT_EN;
540 	    val |= SDHCI_CLOCK_INT_STABLE;
557 			val |= SDHCI_CLOCK_CARD_EN;
559 		val |= SDHCI_CLOCK_CARD_EN;
562 	return (val);
566 fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val)
577 	sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK;
587 		if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
595 		divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
607 		if ((val & SDHCI_CLOCK_CARD_EN) == 0)
609 		divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) |
610 		    ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) <<