dev/qlxgbe/ql_misc.c

63 ql_rdwr_indreg32(qla_host_t *ha, uint32_t addr, uint32_t *val, uint32_t rd)
79 			__func__, addr, *val, rd);
85 		*val = READ_REG32(ha, Q8_WILD_CARD);
87 		WRITE_REG32(ha, Q8_WILD_CARD, *val);
98 ql_rdwr_offchip_mem(qla_host_t *ha, uint64_t addr, q80_offchip_mem_val_t *val,
127 		data = val->data_lo;
133 		data = val->data_hi;
139 		data = val->data_ulo;
145 		data = val->data_uhi;
177 				val->data_lo = data;
184 				val->data_hi = data;
191 				val->data_ulo = data;
198 				val->data_uhi = data;
210 		(uint32_t)(addr), val->data_lo, val->data_hi, val->data_ulo,
211 		val->data_uhi, rd, step);
675 	q80_offchip_mem_val_t val;
685 		ql_rd_flash32(ha, flash_off, &val.data_lo);
689 		ql_rd_flash32(ha, flash_off, &val.data_hi);
693 		ql_rd_flash32(ha, flash_off, &val.data_ulo);
697 		ql_rd_flash32(ha, flash_off, &val.data_uhi);
701 		ql_rdwr_offchip_mem(ha, mem_off, &val, 0);
755         uint32_t val, delay = 300;
765 			val = READ_REG32(ha, Q8_CMDPEG_STATE);
767 			if (val == 0xFF01) {
781 	val = READ_REG32(ha, Q8_CMDPEG_STATE);
782 	if (!cold || (val != 0xFF01) || ha->qla_initiate_recovery) {
1197         q80_offchip_mem_val_t val;
1202                         val.data_lo = *data32++;
1203                         val.data_hi = *data32++;
1204                         val.data_ulo = *data32++;
1205                         val.data_uhi = *data32++;
1207                         if (ql_rdwr_offchip_mem(ha, addr, &val, 0))
1216         bzero(&val, sizeof(q80_offchip_mem_val_t));
1220                 val.data_lo = *data32++;
1221                 val.data_hi = *data32++;
1222                 val.data_ulo = *data32++;
1223                  ret = ql_rdwr_offchip_mem(ha, addr, &val, 0);
1227                 val.data_lo = *data32++;
1228                 val.data_hi = *data32++;
1229                  ret = ql_rdwr_offchip_mem(ha, addr, &val, 0);
1233                 val.data_lo = *data32++;
1234                 ret = ql_rdwr_offchip_mem(ha, addr, &val, 0);