Lines Matching refs:hw
269 CTLFLAG_RD, &ha->hw.mac.xmt_frames,
274 CTLFLAG_RD, &ha->hw.mac.xmt_bytes,
279 CTLFLAG_RD, &ha->hw.mac.xmt_mcast_pkts,
284 CTLFLAG_RD, &ha->hw.mac.xmt_bcast_pkts,
289 CTLFLAG_RD, &ha->hw.mac.xmt_pause_frames,
294 CTLFLAG_RD, &ha->hw.mac.xmt_cntrl_pkts,
299 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_64bytes,
304 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_127bytes,
309 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_255bytes,
314 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_511bytes,
319 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1023bytes,
324 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1518bytes,
329 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_gt_1518bytes,
334 CTLFLAG_RD, &ha->hw.mac.rcv_frames,
339 CTLFLAG_RD, &ha->hw.mac.rcv_bytes,
344 CTLFLAG_RD, &ha->hw.mac.rcv_mcast_pkts,
349 CTLFLAG_RD, &ha->hw.mac.rcv_bcast_pkts,
354 CTLFLAG_RD, &ha->hw.mac.rcv_pause_frames,
359 CTLFLAG_RD, &ha->hw.mac.rcv_cntrl_pkts,
364 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_64bytes,
369 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_127bytes,
374 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_255bytes,
379 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_511bytes,
384 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1023bytes,
389 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1518bytes,
394 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_gt_1518bytes,
399 CTLFLAG_RD, &ha->hw.mac.rcv_len_error,
404 CTLFLAG_RD, &ha->hw.mac.rcv_len_small,
409 CTLFLAG_RD, &ha->hw.mac.rcv_len_large,
414 CTLFLAG_RD, &ha->hw.mac.rcv_jabber,
419 CTLFLAG_RD, &ha->hw.mac.rcv_dropped,
424 CTLFLAG_RD, &ha->hw.mac.fcs_error,
429 CTLFLAG_RD, &ha->hw.mac.align_error,
434 CTLFLAG_RD, &ha->hw.mac.eswitched_frames,
439 CTLFLAG_RD, &ha->hw.mac.eswitched_bytes,
444 CTLFLAG_RD, &ha->hw.mac.eswitched_mcast_frames,
449 CTLFLAG_RD, &ha->hw.mac.eswitched_bcast_frames,
454 CTLFLAG_RD, &ha->hw.mac.eswitched_ucast_frames,
459 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_frames,
464 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_bytes,
486 CTLFLAG_RD, &ha->hw.rcv.total_bytes,
491 CTLFLAG_RD, &ha->hw.rcv.total_pkts,
496 CTLFLAG_RD, &ha->hw.rcv.lro_pkt_count,
501 CTLFLAG_RD, &ha->hw.rcv.sw_pkt_count,
506 CTLFLAG_RD, &ha->hw.rcv.ip_chksum_err,
511 CTLFLAG_RD, &ha->hw.rcv.pkts_wo_acntxts,
516 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_card,
521 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_host,
526 CTLFLAG_RD, &ha->hw.rcv.oversized_pkts,
531 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_rds,
536 CTLFLAG_RD, &ha->hw.rcv.unxpctd_mcast_pkts,
541 CTLFLAG_RD, &ha->hw.rcv.re1_fbq_error,
546 CTLFLAG_RD, &ha->hw.rcv.invalid_mac_addr,
551 CTLFLAG_RD, &ha->hw.rcv.rds_prime_trys,
556 CTLFLAG_RD, &ha->hw.rcv.rds_prime_success,
561 CTLFLAG_RD, &ha->hw.rcv.lro_flows_added,
566 CTLFLAG_RD, &ha->hw.rcv.lro_flows_deleted,
571 CTLFLAG_RD, &ha->hw.rcv.lro_flows_active,
576 CTLFLAG_RD, &ha->hw.rcv.pkts_droped_unknown,
581 CTLFLAG_RD, &ha->hw.rcv.pkts_cnt_oversized,
604 for (i = 0; i < ha->hw.num_tx_rings; i++) {
617 CTLFLAG_RD, &ha->hw.xmt[i].total_bytes,
622 CTLFLAG_RD, &ha->hw.xmt[i].total_pkts,
627 CTLFLAG_RD, &ha->hw.xmt[i].errors,
632 CTLFLAG_RD, &ha->hw.xmt[i].pkts_dropped,
637 CTLFLAG_RD, &ha->hw.xmt[i].switch_pkts,
642 CTLFLAG_RD, &ha->hw.xmt[i].num_buffers,
660 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[0],
665 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[1],
670 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[2],
675 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[3],
680 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[4],
685 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[5],
690 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[6],
695 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[7],
700 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[8],
705 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[9],
710 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[10],
715 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[11],
720 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[12],
725 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[13],
730 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[14],
735 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[15],
740 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[16],
745 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[17],
750 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[18],
783 for (i = 0; i < ha->hw.num_sds_rings; i++) {
794 CTLFLAG_RD, &ha->hw.sds[i].intr_count,
799 CTLFLAG_RD, &ha->hw.sds[i].rx_free,
800 ha->hw.sds[i].rx_free, "rx_free");
822 for (i = 0; i < ha->hw.num_rds_rings; i++) {
833 CTLFLAG_RD, &ha->hw.rds[i].count,
838 CTLFLAG_RD, &ha->hw.rds[i].lro_pkt_count,
843 CTLFLAG_RD, &ha->hw.rds[i].lro_bytes,
867 for (i = 0; i < ha->hw.num_tx_rings; i++) {
914 OID_AUTO, "num_rds_rings", CTLFLAG_RD, &ha->hw.num_rds_rings,
915 ha->hw.num_rds_rings, "Number of Rcv Descriptor Rings");
919 OID_AUTO, "num_sds_rings", CTLFLAG_RD, &ha->hw.num_sds_rings,
920 ha->hw.num_sds_rings, "Number of Status Descriptor Rings");
924 OID_AUTO, "num_tx_rings", CTLFLAG_RD, &ha->hw.num_tx_rings,
925 ha->hw.num_tx_rings, "Number of Transmit Rings");
934 OID_AUTO, "max_tx_segs", CTLFLAG_RD, &ha->hw.max_tx_segs,
935 ha->hw.max_tx_segs, "Max # of Segments in a non-TSO pkt");
937 ha->hw.sds_cidx_thres = 32;
940 OID_AUTO, "sds_cidx_thres", CTLFLAG_RW, &ha->hw.sds_cidx_thres,
941 ha->hw.sds_cidx_thres,
945 ha->hw.rds_pidx_thres = 32;
948 OID_AUTO, "rds_pidx_thres", CTLFLAG_RW, &ha->hw.rds_pidx_thres,
949 ha->hw.rds_pidx_thres,
953 ha->hw.rcv_intr_coalesce = (3 << 16) | 256;
957 &ha->hw.rcv_intr_coalesce,
958 ha->hw.rcv_intr_coalesce,
966 ha->hw.xmt_intr_coalesce = (64 << 16) | 64;
970 &ha->hw.xmt_intr_coalesce,
971 ha->hw.xmt_intr_coalesce,
1010 ha->hw.enable_9kb = 1;
1014 OID_AUTO, "enable_9kb", CTLFLAG_RW, &ha->hw.enable_9kb,
1015 ha->hw.enable_9kb, "Enable 9Kbyte Buffers when MTU = 9000");
1017 ha->hw.enable_hw_lro = 1;
1021 OID_AUTO, "enable_hw_lro", CTLFLAG_RW, &ha->hw.enable_hw_lro,
1022 ha->hw.enable_hw_lro, "Enable Hardware LRO; Default is true \n"
1030 OID_AUTO, "sp_log_index", CTLFLAG_RW, &ha->hw.sp_log_index,
1031 ha->hw.sp_log_index, "sp_log_index");
1035 OID_AUTO, "sp_log_stop", CTLFLAG_RW, &ha->hw.sp_log_stop,
1036 ha->hw.sp_log_stop, "sp_log_stop");
1038 ha->hw.sp_log_stop_events = 0;
1043 &ha->hw.sp_log_stop_events,
1044 ha->hw.sp_log_stop_events, "Slow path event log is stopped"
1052 ha->hw.mdump_active = 0;
1055 OID_AUTO, "minidump_active", CTLFLAG_RW, &ha->hw.mdump_active,
1056 ha->hw.mdump_active,
1059 ha->hw.mdump_done = 0;
1063 &ha->hw.mdump_done, ha->hw.mdump_done,
1066 ha->hw.mdump_capture_mask = 0xF;
1070 &ha->hw.mdump_capture_mask, ha->hw.mdump_capture_mask,
1105 ha->hw.user_pri_nic = 0;
1108 OID_AUTO, "user_pri_nic", CTLFLAG_RW, &ha->hw.user_pri_nic,
1109 ha->hw.user_pri_nic,
1112 ha->hw.user_pri_iscsi = 4;
1115 OID_AUTO, "user_pri_iscsi", CTLFLAG_RW, &ha->hw.user_pri_iscsi,
1116 ha->hw.user_pri_iscsi,
1128 device_printf(ha->pci_dev, "cable_oui\t\t 0x%08x\n", ha->hw.cable_oui);
1130 if (ha->hw.link_up) {
1136 if (ha->hw.fduplex) {
1142 if (ha->hw.autoneg) {
1148 switch (ha->hw.link_speed) {
1166 switch (ha->hw.module_type) {
1183 ha->hw.cable_length);
1189 ha->hw.cable_length);
1196 ha->hw.cable_length);
1222 ha->hw.module_type);
1226 if (ha->hw.link_faults == 1)
1239 if (ha->hw.dma_buf.flags.sds_ring) {
1240 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1241 ql_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]);
1243 ha->hw.dma_buf.flags.sds_ring = 0;
1246 if (ha->hw.dma_buf.flags.rds_ring) {
1247 for (i = 0; i < ha->hw.num_rds_rings; i++) {
1248 ql_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]);
1250 ha->hw.dma_buf.flags.rds_ring = 0;
1253 if (ha->hw.dma_buf.flags.tx_ring) {
1254 ql_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring);
1255 ha->hw.dma_buf.flags.tx_ring = 0;
1269 qla_hw_t *hw;
1278 hw = &ha->hw;
1283 size = (tx_ring_size * ha->hw.num_tx_rings);
1285 hw->dma_buf.tx_ring.alignment = 8;
1286 hw->dma_buf.tx_ring.size = size + PAGE_SIZE;
1288 if (ql_alloc_dmabuf(ha, &hw->dma_buf.tx_ring)) {
1293 vaddr = (uint8_t *)hw->dma_buf.tx_ring.dma_b;
1294 paddr = hw->dma_buf.tx_ring.dma_addr;
1296 for (i = 0; i < ha->hw.num_tx_rings; i++) {
1297 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
1306 for (i = 0; i < ha->hw.num_tx_rings; i++) {
1307 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
1316 ha->hw.dma_buf.flags.tx_ring = 1;
1319 __func__, (void *)(hw->dma_buf.tx_ring.dma_addr),
1320 hw->dma_buf.tx_ring.dma_b));
1325 for (i = 0; i < hw->num_rds_rings; i++) {
1327 hw->dma_buf.rds_ring[i].alignment = 8;
1328 hw->dma_buf.rds_ring[i].size =
1331 if (ql_alloc_dmabuf(ha, &hw->dma_buf.rds_ring[i])) {
1336 ql_free_dmabuf(ha, &hw->dma_buf.rds_ring[j]);
1341 __func__, i, (void *)(hw->dma_buf.rds_ring[i].dma_addr),
1342 hw->dma_buf.rds_ring[i].dma_b));
1345 hw->dma_buf.flags.rds_ring = 1;
1351 for (i = 0; i < hw->num_sds_rings; i++) {
1352 hw->dma_buf.sds_ring[i].alignment = 8;
1353 hw->dma_buf.sds_ring[i].size =
1356 if (ql_alloc_dmabuf(ha, &hw->dma_buf.sds_ring[i])) {
1361 ql_free_dmabuf(ha, &hw->dma_buf.sds_ring[j]);
1367 (void *)(hw->dma_buf.sds_ring[i].dma_addr),
1368 hw->dma_buf.sds_ring[i].dma_b));
1370 for (i = 0; i < hw->num_sds_rings; i++) {
1371 hw->sds[i].sds_ring_base =
1372 (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b;
1375 hw->dma_buf.flags.sds_ring = 1;
1442 ha->hw.mbx_comp_msecs[(Q8_MBX_COMP_MSECS - 2)]++;
1482 ha->hw.mbx_comp_msecs[(Q8_MBX_COMP_MSECS - 1)]++;
1498 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
1506 ha->hw.mbx_comp_msecs[msecs_200]++;
1508 ha->hw.mbx_comp_msecs[15]++;
1512 ha->hw.mbx_comp_msecs[16]++;
1529 bzero(ha->hw.mbox, (sizeof (uint32_t) * Q8_NUM_MBOX));
1531 mbox = ha->hw.mbox;
1567 c_intr = (q80_config_intr_t *)ha->hw.mbox;
1584 ha->hw.intr_id[(start_idx + i)];
1592 ha->hw.mbox, (sizeof (q80_config_intr_rsp_t) >> 2), 0)) {
1598 c_intr_rsp = (q80_config_intr_rsp_t *)ha->hw.mbox;
1619 ha->hw.intr_id[(start_idx + i)] =
1621 ha->hw.intr_src[(start_idx + i)] =
1646 c_rss = (q80_config_rss_t *)ha->hw.mbox;
1675 ha->hw.mbox, (sizeof(q80_config_rss_rsp_t) >> 2), 0)) {
1679 c_rss_rsp = (q80_config_rss_rsp_t *)ha->hw.mbox;
1706 c_rss_ind = (q80_config_rss_ind_table_t *)ha->hw.mbox;
1719 (sizeof (q80_config_rss_ind_table_t) >> 2), ha->hw.mbox,
1725 c_rss_ind_rsp = (q80_config_rss_ind_table_rsp_t *)ha->hw.mbox;
1748 intrc = (q80_config_intr_coalesc_t *)ha->hw.mbox;
1757 intrc->max_pkts = ha->hw.rcv_intr_coalesce & 0xFFFF;
1758 intrc->max_mswait = (ha->hw.rcv_intr_coalesce >> 16) & 0xFFFF;
1761 intrc->max_pkts = ha->hw.xmt_intr_coalesce & 0xFFFF;
1762 intrc->max_mswait = (ha->hw.xmt_intr_coalesce >> 16) & 0xFFFF;
1771 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1779 ha->hw.mbox, (sizeof(q80_config_intr_coalesc_rsp_t) >> 2), 0)) {
1783 intrc_rsp = (q80_config_intr_coalesc_rsp_t *)ha->hw.mbox;
1818 cmac = (q80_config_mac_addr_t *)ha->hw.mbox;
1833 cmac->cntxt_id = ha->hw.rcv_cntxt_id;
1842 ha->hw.mbox, (sizeof(q80_config_mac_addr_rsp_t) >> 2), 1)) {
1847 cmac_rsp = (q80_config_mac_addr_rsp_t *)ha->hw.mbox;
1879 rcv_mode = (q80_config_mac_rcv_mode_t *)ha->hw.mbox;
1888 rcv_mode->cntxt_id = ha->hw.rcv_cntxt_id;
1892 ha->hw.mbox, (sizeof(q80_config_mac_rcv_mode_rsp_t) >> 2), 1)) {
1896 rcv_mode_rsp = (q80_config_mac_rcv_mode_rsp_t *)ha->hw.mbox;
1913 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1914 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1921 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1922 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1930 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_ALL_MULTI_ENABLE;
1931 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1938 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_ALL_MULTI_ENABLE;
1939 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1957 max_mtu = (q80_set_max_mtu_t *)ha->hw.mbox;
1969 ha->hw.mbox, (sizeof (q80_set_max_mtu_rsp_t) >> 2), 1)) {
1974 max_mtu_rsp = (q80_set_max_mtu_rsp_t *)ha->hw.mbox;
1995 lnk = (q80_link_event_t *)ha->hw.mbox;
2006 ha->hw.mbox, (sizeof (q80_link_event_rsp_t) >> 2), 0)) {
2011 lnk_rsp = (q80_link_event_rsp_t *)ha->hw.mbox;
2032 fw_lro = (q80_config_fw_lro_t *)ha->hw.mbox;
2046 ha->hw.mbox, (sizeof (q80_config_fw_lro_rsp_t) >> 2), 0)) {
2051 fw_lro_rsp = (q80_config_fw_lro_rsp_t *)ha->hw.mbox;
2072 hw_config = (q80_hw_config_t *)ha->hw.mbox;
2085 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
2089 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
2110 hw_config = (q80_hw_config_t *)ha->hw.mbox;
2121 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
2125 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
2149 stat = (q80_get_stats_t *)ha->hw.mbox;
2159 ha->hw.mbox, (rsp_size >> 2), 0)) {
2164 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
2199 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
2214 bcopy(mstat, &ha->hw.mac, sizeof(q80_mac_stats_t));
2217 __func__, ha->hw.mbox[0]);
2224 cmd |= (ha->hw.rcv_cntxt_id << 16);
2232 bcopy(rstat, &ha->hw.rcv, sizeof(q80_rcv_stats_t));
2235 __func__, ha->hw.mbox[0]);
2244 for (i = 0 ; (i < ha->hw.num_tx_rings); i++) {
2252 cmd |= (ha->hw.tx_cntxt[i].tx_cntxt_id << 16);
2257 bcopy(xstat, &ha->hw.xmt[i], sizeof(q80_xmt_stats_t));
2260 __func__, ha->hw.mbox[0]);
2499 qla_hw_t *hw = &ha->hw;
2563 if (hw->tx_cntxt[txr_idx].txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) {
2565 if (hw->tx_cntxt[txr_idx].txr_free <=
2567 QL_DPRINT8(ha, (dev, "%s: (hw->txr_free <= "
2588 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[tx_idx];
2592 if (nsegs > ha->hw.max_tx_segs)
2593 ha->hw.max_tx_segs = nsegs;
2613 eh->evl_tag |= ha->hw.user_pri_iscsi << 13;
2628 tx_cmd->vlan_tci |= ha->hw.user_pri_iscsi << 13;
2670 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2671 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2678 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2686 txr_next = hw->tx_cntxt[txr_idx].txr_next;
2688 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2724 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2725 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2730 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2739 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2740 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2746 hw->tx_cntxt[txr_idx].txr_free =
2747 hw->tx_cntxt[txr_idx].txr_free - tx_cmd_count;
2749 QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->tx_cntxt[txr_idx].txr_next,\
2767 rss_ind_tbl[i] = i % ha->hw.num_sds_rings;
2779 if (qla_set_rss_ind_table(ha, i, count, ha->hw.rcv_cntxt_id,
2791 qla_hw_t *hw = &ha->hw;
2794 for (i = 0; i < hw->num_sds_rings; i++) {
2795 lro = &hw->sds[i].lro;
2826 qla_hw_t *hw = &ha->hw;
2829 for (i = 0; i < hw->num_sds_rings; i++) {
2830 lro = &hw->sds[i].lro;
2852 qla_hw_t *hw = &ha->hw;
2855 for (i = 0; i < hw->num_sds_rings; i++) {
2856 lro = &hw->sds[i].lro;
2882 if (ha->hw.flags.init_intr_cnxt) {
2883 for (i = 0; i < ha->hw.num_sds_rings; ) {
2885 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2888 num_msix = ha->hw.num_sds_rings - i;
2896 ha->hw.flags.init_intr_cnxt = 0;
2900 if (ha->hw.enable_soft_lro) {
2913 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX);
2917 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
2924 ha->hw.enable_9kb = 0;
2946 for (i = 0; i < ha->hw.num_sds_rings; i++) {
2947 bzero(ha->hw.dma_buf.sds_ring[i].dma_b,
2948 ha->hw.dma_buf.sds_ring[i].size);
2951 for (i = 0; i < ha->hw.num_sds_rings; ) {
2953 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2956 num_msix = ha->hw.num_sds_rings - i;
2976 ha->hw.flags.init_intr_cnxt = 1;
2985 for (i = 0; i < ha->hw.num_rds_rings; i++) {
2986 rdesc = &ha->hw.rds[i];
3001 ha->hw.max_tx_segs = 0;
3003 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 1, 1))
3006 ha->hw.flags.unicast_mac = 1;
3014 ha->hw.flags.bcast_mac = 1;
3022 if (ql_set_max_mtu(ha, ha->max_frame_size, ha->hw.rcv_cntxt_id))
3025 if (qla_config_rss(ha, ha->hw.rcv_cntxt_id))
3031 if (qla_config_intr_coalesce(ha, ha->hw.rcv_cntxt_id, 0, 1))
3034 if (qla_link_event_req(ha, ha->hw.rcv_cntxt_id))
3038 if (ha->hw.enable_hw_lro) {
3039 ha->hw.enable_soft_lro = 0;
3041 if (qla_config_fw_lro(ha, ha->hw.rcv_cntxt_id))
3044 ha->hw.enable_soft_lro = 1;
3057 for (i = 0; i < ha->hw.num_sds_rings; i++)
3070 qla_hw_t *hw = &ha->hw;
3072 map_rings = (q80_rq_map_sds_to_rds_t *)ha->hw.mbox;
3079 map_rings->cntxt_id = hw->rcv_cntxt_id;
3089 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
3094 map_rings_rsp = (q80_rsp_map_sds_to_rds_t *)ha->hw.mbox;
3117 qla_hw_t *hw = &ha->hw;
3130 for (i = 0; i < hw->num_sds_rings; i++) {
3131 sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0];
3139 rcntxt_sds_rings = hw->num_sds_rings;
3140 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS)
3143 rcntxt_rds_rings = hw->num_rds_rings;
3145 if (hw->num_rds_rings > MAX_RDS_RING_SETS)
3148 rcntxt = (q80_rq_rcv_cntxt_t *)ha->hw.mbox;
3161 if (ha->hw.enable_9kb)
3166 if (ha->hw.num_rds_rings > 1) {
3180 qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr);
3183 rcntxt->sds[i].intr_id = qla_host_to_le16(hw->intr_id[i]);
3189 qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr);
3191 if (ha->hw.enable_9kb)
3203 ha->hw.mbox, (sizeof(q80_rsp_rcv_cntxt_t) >> 2), 0)) {
3208 rcntxt_rsp = (q80_rsp_rcv_cntxt_t *)ha->hw.mbox;
3218 hw->sds[i].sds_consumer = rcntxt_rsp->sds_cons[i];
3222 hw->rds[i].prod_std = rcntxt_rsp->rds[i].prod_std;
3225 hw->rcv_cntxt_id = rcntxt_rsp->cntxt_id;
3227 ha->hw.flags.init_rx_cnxt = 1;
3229 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) {
3231 for (i = MAX_RCNTXT_SDS_RINGS; i < hw->num_sds_rings;) {
3233 if ((i + MAX_RCNTXT_SDS_RINGS) < hw->num_sds_rings)
3236 max_idx = hw->num_sds_rings - i;
3246 if (hw->num_rds_rings > 1) {
3248 for (i = 0; i < hw->num_rds_rings; ) {
3250 if ((i + MAX_SDS_TO_RDS_MAP) < hw->num_rds_rings)
3253 max_idx = hw->num_rds_rings - i;
3273 qla_hw_t *hw = &ha->hw;
3275 add_rcv = (q80_rq_add_rcv_rings_t *)ha->hw.mbox;
3284 add_rcv->cntxt_id = hw->rcv_cntxt_id;
3291 qla_host_to_le64(hw->dma_buf.sds_ring[j].dma_addr);
3296 add_rcv->sds[i].intr_id = qla_host_to_le16(hw->intr_id[j]);
3305 qla_host_to_le64(hw->dma_buf.rds_ring[j].dma_addr);
3307 if (ha->hw.enable_9kb)
3320 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
3325 add_rcv_rsp = (q80_rsp_add_rcv_rings_t *)ha->hw.mbox;
3335 hw->sds[(i + sds_idx)].sds_consumer = add_rcv_rsp->sds_cons[i];
3339 hw->rds[(i + sds_idx)].prod_std = add_rcv_rsp->rds[i].prod_std;
3358 if (!ha->hw.flags.init_rx_cnxt)
3364 if (ha->hw.flags.bcast_mac) {
3371 ha->hw.flags.bcast_mac = 0;
3375 if (ha->hw.flags.unicast_mac) {
3376 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 0, 1))
3378 ha->hw.flags.unicast_mac = 0;
3381 rcntxt = (q80_rcv_cntxt_destroy_t *)ha->hw.mbox;
3388 rcntxt->cntxt_id = ha->hw.rcv_cntxt_id;
3392 ha->hw.mbox, (sizeof(q80_rcv_cntxt_destroy_rsp_t) >> 2), 0)) {
3396 rcntxt_rsp = (q80_rcv_cntxt_destroy_rsp_t *)ha->hw.mbox;
3404 ha->hw.flags.init_rx_cnxt = 0;
3416 qla_hw_t *hw = &ha->hw;
3423 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
3430 tcntxt = (q80_rq_tx_cntxt_t *)ha->hw.mbox;
3444 if (txr_idx >= (ha->hw.num_tx_rings >> 1)) {
3448 intr_idx = txr_idx % (ha->hw.num_tx_rings >> 1);
3463 tcntxt->tx_ring[0].intr_id = qla_host_to_le16(hw->intr_id[intr_idx]);
3472 ha->hw.mbox,
3477 tcntxt_rsp = (q80_rsp_tx_cntxt_t *)ha->hw.mbox;
3508 tcntxt = (q80_tx_cntxt_destroy_t *)ha->hw.mbox;
3515 tcntxt->cntxt_id = ha->hw.tx_cntxt[txr_idx].tx_cntxt_id;
3519 ha->hw.mbox, (sizeof (q80_tx_cntxt_destroy_rsp_t) >> 2), 0)) {
3523 tcntxt_rsp = (q80_tx_cntxt_destroy_rsp_t *)ha->hw.mbox;
3540 if (!ha->hw.flags.init_tx_cnxt)
3543 for (i = 0; i < ha->hw.num_tx_rings; i++) {
3547 ha->hw.flags.init_tx_cnxt = 0;
3557 for (i = 0; i < ha->hw.num_tx_rings; i++) {
3566 ha->hw.flags.init_tx_cnxt = 1;
3577 nmcast = ha->hw.nmcast;
3582 mcast = ha->hw.mac_addr_arr;
3586 if ((ha->hw.mcast[i].addr[0] != 0) ||
3587 (ha->hw.mcast[i].addr[1] != 0) ||
3588 (ha->hw.mcast[i].addr[2] != 0) ||
3589 (ha->hw.mcast[i].addr[3] != 0) ||
3590 (ha->hw.mcast[i].addr[4] != 0) ||
3591 (ha->hw.mcast[i].addr[5] != 0)) {
3593 bcopy(ha->hw.mcast[i].addr, mcast, ETHER_ADDR_LEN);
3599 __func__, ha->hw.mcast[i].addr[0],
3600 ha->hw.mcast[i].addr[1], ha->hw.mcast[i].addr[2],
3601 ha->hw.mcast[i].addr[3], ha->hw.mcast[i].addr[4],
3602 ha->hw.mcast[i].addr[5]);
3605 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3613 mcast = ha->hw.mac_addr_arr;
3623 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mcast,
3652 bzero(ha->hw.mcast, (sizeof (qla_mcast_t) * Q8_MAX_NUM_MULTICAST_ADDRS));
3653 ha->hw.nmcast = 0;
3664 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0)
3677 if ((ha->hw.mcast[i].addr[0] == 0) &&
3678 (ha->hw.mcast[i].addr[1] == 0) &&
3679 (ha->hw.mcast[i].addr[2] == 0) &&
3680 (ha->hw.mcast[i].addr[3] == 0) &&
3681 (ha->hw.mcast[i].addr[4] == 0) &&
3682 (ha->hw.mcast[i].addr[5] == 0)) {
3684 bcopy(mta, ha->hw.mcast[i].addr, Q8_MAC_ADDR_LEN);
3685 ha->hw.nmcast++;
3704 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) {
3706 ha->hw.mcast[i].addr[0] = 0;
3707 ha->hw.mcast[i].addr[1] = 0;
3708 ha->hw.mcast[i].addr[2] = 0;
3709 ha->hw.mcast[i].addr[3] = 0;
3710 ha->hw.mcast[i].addr[4] = 0;
3711 ha->hw.mcast[i].addr[5] = 0;
3713 ha->hw.nmcast--;
3740 mcast = ha->hw.mac_addr_arr;
3760 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3768 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr,
3771 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr,
3776 mcast = ha->hw.mac_addr_arr;
3784 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mac,
3790 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, count);
3792 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, count);
3807 qla_hw_t *hw = &ha->hw;
3811 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
3860 prev_link_state = ha->hw.link_up;
3872 atomic_store_rel_8(&ha->hw.link_up, (uint8_t)link_state);
3874 if (prev_link_state != ha->hw.link_up) {
3875 if (ha->hw.link_up) {
3889 ha->hw.health_count++;
3891 if (ha->hw.health_count < 500)
3894 ha->hw.health_count = 0;
3904 if (ha->hw.sp_log_stop_events & Q8_SP_LOG_STOP_TEMP_FAILURE)
3905 ha->hw.sp_log_stop = -1;
3913 if ((val != ha->hw.hbeat_value) &&
3915 ha->hw.hbeat_value = val;
3916 ha->hw.hbeat_failure = 0;
3920 ha->hw.hbeat_failure++;
3923 if ((ha->dbg_level & 0x8000) && (ha->hw.hbeat_failure == 1))
3926 if (ha->hw.hbeat_failure < 2) /* we ignore the first failure */
3943 if (ha->hw.sp_log_stop_events & Q8_SP_LOG_STOP_HBEAT_FAILURE)
3944 ha->hw.sp_log_stop = -1;
3961 init_nic = (q80_init_nic_func_t *)ha->hw.mbox;
3975 ha->hw.mbox, (sizeof (q80_init_nic_func_rsp_t) >> 2), 0)) {
3980 init_nic_rsp = (q80_init_nic_func_rsp_t *)ha->hw.mbox;
4004 stop_nic = (q80_stop_nic_func_t *)ha->hw.mbox;
4017 ha->hw.mbox, (sizeof (q80_stop_nic_func_rsp_t) >> 2), 0)) {
4022 stop_nic_rsp = (q80_stop_nic_func_rsp_t *)ha->hw.mbox;
4044 fw_dcbx = (q80_query_fw_dcbx_caps_t *)ha->hw.mbox;
4054 ha->hw.mbox, (sizeof (q80_query_fw_dcbx_caps_rsp_t) >> 2), 0)) {
4059 fw_dcbx_rsp = (q80_query_fw_dcbx_caps_rsp_t *)ha->hw.mbox;
4084 idc_ack = (q80_idc_ack_t *)ha->hw.mbox;
4096 ha->hw.imd_compl= 0;
4100 ha->hw.mbox, (sizeof (q80_idc_ack_rsp_t) >> 2), 0)) {
4105 idc_ack_rsp = (q80_idc_ack_rsp_t *)ha->hw.mbox;
4114 while (count && !ha->hw.imd_compl) {
4138 pcfg = (q80_set_port_cfg_t *)ha->hw.mbox;
4154 ha->hw.imd_compl= 0;
4158 ha->hw.mbox, (sizeof (q80_set_port_cfg_rsp_t) >> 2), 0)) {
4163 pfg_rsp = (q80_set_port_cfg_rsp_t *)ha->hw.mbox;
4168 while (count && !ha->hw.imd_compl) {
4206 md_size = (q80_config_md_templ_size_t *) ha->hw.mbox;
4214 (sizeof(q80_config_md_templ_size_t) >> 2), ha->hw.mbox,
4222 md_size_rsp = (q80_config_md_templ_size_rsp_t *) ha->hw.mbox;
4246 pcfg = (q80_get_port_cfg_t *)ha->hw.mbox;
4255 ha->hw.mbox, (sizeof (q80_get_port_cfg_rsp_t) >> 2), 0)) {
4260 pcfg_rsp = (q80_get_port_cfg_rsp_t *)ha->hw.mbox;
4365 switch (ha->hw.aen_mb0) {
4367 (void)qla_idc_ack(ha, ha->hw.aen_mb1, ha->hw.aen_mb2,
4368 ha->hw.aen_mb3, ha->hw.aen_mb4);
4388 md_templ = (q80_config_md_templ_cmd_t *) ha->hw.mbox;
4395 md_templ->buf_addr = ha->hw.dma_buf.minidump.dma_addr;
4396 md_templ->buff_size = ha->hw.dma_buf.minidump.size;
4400 ha->hw.mbox,
4408 md_templ_rsp = (q80_config_md_templ_cmd_rsp_t *) ha->hw.mbox;
4484 hdr = (ql_minidump_template_hdr_t *)ha->hw.dma_buf.minidump.dma_b;
4489 if (i & ha->hw.mdump_capture_mask)
4499 if (ha->hw.mdump_buffer != NULL) {
4500 free(ha->hw.mdump_buffer, M_QLA83XXBUF);
4501 ha->hw.mdump_buffer = NULL;
4502 ha->hw.mdump_buffer_size = 0;
4510 ha->hw.mdump_buffer_size = ql_minidump_size(ha);
4512 if (!ha->hw.mdump_buffer_size)
4515 ha->hw.mdump_buffer = malloc(ha->hw.mdump_buffer_size, M_QLA83XXBUF,
4518 if (ha->hw.mdump_buffer == NULL)
4527 if (ha->hw.mdump_template != NULL) {
4528 free(ha->hw.mdump_template, M_QLA83XXBUF);
4529 ha->hw.mdump_template = NULL;
4530 ha->hw.mdump_template_size = 0;
4538 ha->hw.mdump_template_size = ha->hw.dma_buf.minidump.size;
4540 ha->hw.mdump_template = malloc(ha->hw.mdump_template_size,
4543 if (ha->hw.mdump_template == NULL)
4575 count = ha->hw.dma_buf.minidump.size / sizeof (uint32_t);
4576 template_buff = ha->hw.dma_buf.minidump.dma_b;
4611 ha->hw.dma_buf.minidump.alignment = 8;
4612 ha->hw.dma_buf.minidump.size = template_size;
4615 if (ql_alloc_dmabuf(ha, &ha->hw.dma_buf.minidump)) {
4621 ha->hw.dma_buf.flags.minidump = 1;
4628 ha->hw.dma_buf.minidump.dma_b = ql83xx_minidump;
4641 ha->hw.mdump_init = 1;
4664 ha->hw.mdump_init = 0;
4665 if (ha->hw.dma_buf.flags.minidump) {
4666 ha->hw.dma_buf.flags.minidump = 0;
4667 ql_free_dmabuf(ha, &ha->hw.dma_buf.minidump);
4679 if (!ha->hw.mdump_init)
4682 if (ha->hw.mdump_done)
4684 ha->hw.mdump_usec_ts = qla_get_usec_timestamp();
4685 ha->hw.mdump_start_seq_index = ql_stop_sequence(ha);
4687 bzero(ha->hw.mdump_buffer, ha->hw.mdump_buffer_size);
4688 bzero(ha->hw.mdump_template, ha->hw.mdump_template_size);
4690 bcopy(ha->hw.dma_buf.minidump.dma_b, ha->hw.mdump_template,
4691 ha->hw.mdump_template_size);
4695 ql_start_sequence(ha, ha->hw.mdump_start_seq_index);
4697 ha->hw.mdump_done = 1;
4730 template_hdr = (ql_minidump_template_hdr_t *)ha->hw.mdump_template;
4735 dump_buff = (char *) ha->hw.mdump_buffer;
4746 capture_mask = ha->hw.mdump_capture_mask;
4747 dump_size = ha->hw.mdump_buffer_size;