dev/qlxgb/qla_misc.c

204 qla_rdwr_indreg32(qla_host_t *ha, uint32_t addr, uint32_t *val, uint32_t rd)
244 		*val = READ_OFFSET32(ha, ((addr & 0xFFFF) | 0x1E0000));
246 		WRITE_OFFSET32(ha, ((addr & 0xFFFF) | 0x1E0000), *val);
258 qla_rdwr_offchip_mem(qla_host_t *ha, uint64_t addr, offchip_mem_val_t *val,
268 		WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_LO, val->data_lo);
269 		WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_HI, val->data_hi);
270 		WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_ULO, val->data_ulo);
271 		WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_UHI, val->data_uhi);
281 				val->data_lo = READ_OFFSET32(ha, \
283 				val->data_hi = READ_OFFSET32(ha, \
285 				val->data_ulo = READ_OFFSET32(ha, \
287 				val->data_uhi = READ_OFFSET32(ha, \
306 	uint32_t val;
315 	val = addr;
316 	qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);
317 	val = 0;
318 	qla_rdwr_indreg32(ha, Q8_ROM_DUMMY_BYTE_COUNT, &val, 0);
319 	val = 3;
320 	qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
324 	val = ROM_OPCODE_FAST_RD;
325 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
327 	while (!((val = READ_OFFSET32(ha, Q8_ROM_STATUS)) & BIT_1)) {
335 	val = 0;
336 	qla_rdwr_indreg32(ha, Q8_ROM_DUMMY_BYTE_COUNT, &val, 0);
337 	qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
416 	uint32_t val = 0, sig = 0;
421 	QL_DPRINT2((ha->pci_dev, "%s: val[0] = 0x%08x\n", __func__, sig));
423 	qla_rd_flash32(ha, 4, &val);
424 	QL_DPRINT2((ha->pci_dev, "%s: val[4] = 0x%08x\n", __func__, val));
426 	count = val >> 16;
427 	offset = val & 0xFFFF;
430 	QL_DPRINT2((ha->pci_dev, "%s: [sig,val]=[0x%08x, 0x%08x] %d pairs\n",
431 		__func__, sig, val, count));
500 	offchip_mem_val_t val;
505 		qla_rd_flash32(ha, flash_off, &val.data_lo);
509 		qla_rd_flash32(ha, flash_off, &val.data_hi);
513 		qla_rd_flash32(ha, flash_off, &val.data_ulo);
517 		qla_rd_flash32(ha, flash_off, &val.data_uhi);
521 		qla_rdwr_offchip_mem(ha, mem_off, &val, 0);
596         uint32_t val, delay = 300;
606 			val = READ_OFFSET32(ha, Q8_CMDPEG_STATE);
608 			if (val == CMDPEG_PHAN_INIT_COMPLETE) {
620 	val = READ_OFFSET32(ha, Q8_CMDPEG_STATE);
622 	if (val != CMDPEG_PHAN_INIT_COMPLETE) {
630 		if (qla_rd_flash32(ha, 0x100004, &val) == 0) {
632 			if (((val & 0xFF) != ha->fw_ver_major) ||
633 				(((val >> 8) & 0xFF) != ha->fw_ver_minor) ||
634 				(((val >> 16) & 0xFF) != ha->fw_ver_sub)) {
655 	uint32_t val;
660 		val = READ_OFFSET32(ha, Q8_ROM_STATUS);
662 		if (val & BIT_1)
672 	uint32_t val, rval;
674 	val = 0;
675 	qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
677 	val = ROM_OPCODE_WR_ENABLE;
678 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
691 	uint32_t val, rval;
696 	val = 0;
697 	qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);
699 	val = ROM_OPCODE_WR_STATUS_REG;
700 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
712 	val = 0;
713 	qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);
715 	val = ROM_OPCODE_WR_STATUS_REG;
716 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
729 	uint32_t val, rval;
734 	val = 0x9C;
735 	qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);
737 	val = ROM_OPCODE_WR_STATUS_REG;
738 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
752 	uint32_t val, rval;
755 		val = 0;
756 		qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
758 		val = ROM_OPCODE_RD_STATUS_REG;
759 		qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
764 			qla_rdwr_indreg32(ha, Q8_ROM_RD_DATA, &val, 1);
766 			if ((val & BIT_0) == 0)
767 				return (val);
809 	uint32_t val;
815         val = start;
816         qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);
818         val = 3;
819         qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
821         val = ROM_OPCODE_SECTOR_ERASE;
822         qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
869 	uint32_t val;
872         val = data;
873         qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);
875         val = off;
876         qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);
878         val = 3;
879         qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
881         val = ROM_OPCODE_PROG_PAGE;
882         qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
895 	uint32_t val, count = 1000;
900 		val = 0;
901 		qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
903 		val = ROM_OPCODE_RD_STATUS_REG;
904 		qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
910 			qla_rdwr_indreg32(ha, Q8_ROM_RD_DATA, &val, 1);
912 			if ((val & BIT_0) == 0)