Lines Matching refs:TSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5

87921   #define TSEM_REG_INT_MASK_0_PB_QUE_ARB_QUEUES_ERROR_E5                                                     (0x1<<20) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.PB_QUE_ARB_QUEUES_ERROR .