Lines Matching refs:PTU_REG_ATC_IREQ_ALMOST_FULL_THR

64500 #define PTU_REG_ATC_IREQ_ALMOST_FULL_THR                                                                     0x560454UL //Access:RW   DataWidth:0x8    // Debug only: defines the IFIFO almost full threshold. Its size can't be bigger than the Ireq FIFO size. The full resp delay of the interface is 4. There is a problem with the implementation and the real value the FIFO can absorbe is 1 below the configured value, but 4 request still can be received when the register configured to 6