Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_K2_E5
33511 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_K2_E5 0x002014UL //Access:RW DataWidth:0x8 // Multi Field Register.