Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_BIT_O_K2_E5

33305   #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_BIT_O_K2_E5                                              (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.