Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_K2_E5
32261 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_K2_E5 0x0014c0UL //Access:RW DataWidth:0x8 // Multi Field Register.