Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXN_MARGIN_K2_E5
31699 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXN_MARGIN_K2_E5 (0xf<<4) // Value to minus/add from the calibrated txterm value