Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O_K2_E5
30277 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O_K2_E5 (0x3<<0) // Rate control for BIST