Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5
30429 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5 (0x7<<3) // Number of clock cycles between signal detect indicator