Lines Matching refs:PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5

30889   #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_K2_E5                            (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]