Lines Matching refs:PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X217_K2_E5

35288 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X217_K2_E5                                                         0x002b64UL //Access:RW   DataWidth:0x8    // DFE block - ATT calibration cycle length. This is the number of cycles the DFE will wait between changing the ATT value and examining the output.