Lines Matching refs:PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5
34907 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_K2_E5 (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode