Lines Matching refs:PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_K2_E5

29764   #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_K2_E5                                (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment