Lines Matching refs:PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_CLEAR_K2_E5
17776 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_CLEAR_K2_E5 (0x1<<3) // Synchronous reset for LT Tx block.