Lines Matching refs:PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT1_BB

5939   #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT1_BB                                                       (0x1<<13) // This bits is set when h/w detects Receive UR Status in function 1. If set, h/w generates pcie_err_attn output .