Lines Matching refs:PCIEIP_REG_TL_CONTROL_2_CTS0_MASK_BB

5786   #define PCIEIP_REG_TL_CONTROL_2_CTS0_MASK_BB                                                               (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.