Lines Matching refs:PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_K2

4564   #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_K2                                           (0x1<<20) // Up to 64GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.