Lines Matching refs:PCIEIP_REG_REG_RC_USER_MEM_HI1_BB

5092 #define PCIEIP_REG_REG_RC_USER_MEM_HI1_BB                                                                    0x00055cUL //Access:R    DataWidth:0x20   // USER_BAR_HIGHER_ADDRESS: Higher 32 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.