Lines Matching refs:PCIEIP_REG_REG_PHY_CTL_1_REG_POWERDOWN_P1PLL_ENA_BB

8044   #define PCIEIP_REG_REG_PHY_CTL_1_REG_POWERDOWN_P1PLL_ENA_BB                                                (0x1<<12) // This signal goes to the PCIe Serdes to enable the PLL to power down when all lanes are in L1 If ClkReq is active, this signal is ignored.