Lines Matching refs:PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_PARA_BB

7540   #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_PARA_BB                                                        (0x1<<10) // When set, this indicates the FIFOs are linked in parallel to increase the width of the FIFO.